[RFC v5 05/12] dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding

[Rob Herring]

On Wed, Nov 04, 2015 at 12:45:02PM +0100, Philipp Zabel wrote:
> Add the device tree binding documentation for Mediatek HDMI,
> HDMI PHY and HDMI DDC devices.
> 
> Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>

Acked-by: Rob Herring <robh at kernel.org>

> ---
> Changes since v4:
>  - Remove mediatek,cec and ddc-i2c-bus from hdmi node
>  - Make output port required
>  - Add mediatek, prefix to phy node current bias
>    properties
> ---
>  .../bindings/display/mediatek/mediatek,hdmi.txt    | 142 +++++++++++++++++++++
>  1 file changed, 142 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> new file mode 100644
> index 0000000..e3dde29
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> @@ -0,0 +1,142 @@
> +Mediatek HDMI Encoder
> +=====================
> +
> +The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
> +its parallel input.
> +
> +Required properties:
> +- compatible: Should be "mediatek,<chip>-hdmi".
> +- reg: Physical base address and length of the controller's registers
> +- interrupts: The interrupt signal from the function block.
> +- clocks: device clocks
> +  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
> +- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
> +- phys: phandle link to the HDMI PHY node.
> +  See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
> +- phy-names: must contain "hdmi"
> +- mediatek,syscon-hdmi: phandle link and register offset to the system
> +  configuration registers. For mt8173 this must be offset 0x900 into the
> +  MMSYS_CONFIG region: <&mmsys 0x900>.
> +- ports: A node containing input and output port nodes with endpoint
> +  definitions as documented in Documentation/devicetree/bindings/graph.txt.
> +- port at 0: The input port in the ports node should be connected to a DPI output
> +  port.
> +- port at 1: The output port in the ports node should be connected to the input
> +  port of a connector node that contains a ddc-i2c-bus property, or to the
> +  input port of an attached bridge chip, such as a SlimPort transmitter.
> +
> +HDMI CEC
> +========
> +
> +The HDMI CEC controller handles hotplug detection and CEC communication.
> +
> +Required properties:
> +- compatible: Should be "mediatek,<chip>-cec"
> +- reg: Physical base address and length of the controller's registers
> +- interrupts: The interrupt signal from the function block.
> +- clocks: device clock
> +
> +HDMI DDC
> +========
> +
> +The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
> +The Mediatek's I2C controller is used to interface with I2C devices.
> +
> +Required properties:
> +- compatible: Should be "mediatek,<chip>-hdmi-ddc"
> +- reg: Physical base address and length of the controller's registers
> +- clocks: device clock
> +- clock-names: Should be "ddc-i2c".
> +
> +HDMI PHY
> +========
> +
> +The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
> +output and drives the HDMI pads.
> +
> +Required properties:
> +- compatible: "mediatek,<chip>-hdmi-phy"
> +- reg: Physical base address and length of the module's registers
> +- clocks: PLL reference clock
> +- clock-names: must contain "pll_ref"
> +- #phy-cells: must be <0>.
> +
> +Optional properties:
> +- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
> +- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
> +
> +Example:
> +
> +cec: cec at 10013000 {
> +	compatible = "mediatek,mt8173-cec";
> +	reg = <0 0x10013000 0 0xbc>;
> +	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
> +	clocks = <&infracfg CLK_INFRA_CEC>;
> +};
> +
> +hdmi_phy: hdmi-phy at 10209100 {
> +	compatible = "mediatek,mt8173-hdmi-phy";
> +	reg = <0 0x10209100 0 0x24>;
> +	clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
> +	clock-names = "pll_ref";
> +	mediatek,ibias = <0xa>;
> +	mediatek,ibias_up = <0x1c>;
> +	#phy-cells = <0>;
> +};
> +
> +hdmi_ddc0: i2c at 11012000 {
> +	compatible = "mediatek,mt8173-hdmi-ddc";
> +	reg = <0 0x11012000 0 0x1c>;
> +	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
> +	clocks = <&pericfg CLK_PERI_I2C5>;
> +	clock-names = "ddc-i2c";
> +};
> +
> +hdmi0: hdmi at 14025000 {
> +	compatible = "mediatek,mt8173-hdmi";
> +	reg = <0 0x14025000 0 0x400>;
> +	interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
> +	clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
> +		 <&mmsys CLK_MM_HDMI_PLLCK>,
> +		 <&mmsys CLK_MM_HDMI_AUDIO>,
> +		 <&mmsys CLK_MM_HDMI_SPDIF>;
> +	clock-names = "pixel", "pll", "bclk", "spdif";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&hdmi_pin>;
> +	phys = <&hdmi_phy>;
> +	phy-names = "hdmi";
> +	mediatek,syscon-hdmi = <&mmsys 0x900>;
> +
> +	ports {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		port at 0 {
> +			reg = <0>;
> +
> +			hdmi0_in: endpoint {
> +				remote-endpoint = <&dpi0_out>;
> +			};
> +		};
> +
> +		port at 1 {
> +			reg = <1>;
> +
> +			hdmi0_out: endpoint {
> +				remote-endpoint = <&hdmi_con_in>;
> +			};
> +		};
> +	};
> +};
> +
> +connector {
> +	compatible = "hdmi-connector";
> +	type = "a";
> +	ddc-i2c-bus = <&hdmiddc0>;
> +
> +	port {
> +		hdmi_con_in: endpoint {
> +			remote-endpoint = <&hdmi0_out>;
> +		};
> +	};
> +};
> -- 
> 2.6.1
>