[PATCH v3 2/3] clk: mediatek: Fix calculation of PLL rate settings
Stephen Boyd
sboyd at codeaurora.org
Fri Jul 17 17:47:53 PDT 2015
On 07/10, James Liao wrote:
> Avoid u32 overflow when calculate post divider setting, and
> increase the max post divider setting from 3 (/8) to 4 (/16).
>
> Signed-off-by: James Liao <jamesjj.liao at mediatek.com>
> ---
Applied to clk-next
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