[PATCH v4 3/3] i3c: master: amd: Add hot-join support

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The driver fails to clear `XI3C_CR_HJ_MASK` and `XI3C_CR_IBI_MASK` from the Core Control Register (`XI3C_CR_OFFSET`) during controller initialization. When the controller is subsequently enabled, any previously set bits (e.g., from a warm boot, kexec, or bootloader) remain active. This causes the controller to silently ACK hot-join or IBI requests on the bus without generating interrupts (since `XI3C_INTR_RE_OFFSET` is zeroed), irrevocably stalling bus enumeration.
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commit 2fc8cea47a914e1d8d7312826561a084f785d035
Author: Shubham Patil <shubhamsanjay.patil at amd.com>
Subject: i3c: master: amd: Add hot-join support

This commit adds hot-join support for the AMD AXI I3C master controller.
It introduces sysfs-based configuration and handles events via the i3c core
hot-join queue to run DAA for enumerating new devices.

> diff --git a/drivers/i3c/master/amd-i3c-master.c b/drivers/i3c/master/amd-i3c-master.c
> index a50445530a430..400bf15e02992 100644
> --- a/drivers/i3c/master/amd-i3c-master.c
> +++ b/drivers/i3c/master/amd-i3c-master.c

[ ... ]

> @@ -1244,13 +1250,14 @@ static void xi3c_master_bus_cleanup(struct i3c_master_controller *m)
>  	struct xi3c_master *master = to_xi3c_master(m);
>  
>  	/*
> -	 * Disarm all interrupt sources and the IBI ACK so the controller can't
> -	 * assert once disabled; reset the refcount that tracks them.
> +	 * Disarm the interrupts and the IBI/Hot-Join ACKs so nothing is left
> +	 * armed for a later bus_init(); reset the refcount that tracks them.
>  	 */
>  	scoped_guard(spinlock_irqsave, &master->reg_lock) {
>  		iowrite32(0, master->membase + XI3C_INTR_RE_OFFSET);
>  		iowrite32(ioread32(master->membase + XI3C_CR_OFFSET) &
> -			  ~XI3C_CR_IBI_MASK, master->membase + XI3C_CR_OFFSET);
> +			  ~(XI3C_CR_IBI_MASK | XI3C_CR_HJ_MASK),
> +			  master->membase + XI3C_CR_OFFSET);
>  		master->ibi.enabled_count = 0;
>  	}

[Severity: High]
Does xi3c_master_init() also need to clear these masks from XI3C_CR_OFFSET to
guarantee a clean state before enabling the controller?

If the controller is enabled after a warm boot or kexec where a bootloader
left the Hot-Join bit active, the driver currently fails to clear it in
xi3c_master_init():

drivers/i3c/master/amd-i3c-master.c:xi3c_master_init() {
	/* Mask all interrupt sources and clear any stale latched events. */
	iowrite32(0, master->membase + XI3C_INTR_RE_OFFSET);
	iowrite32(ioread32(master->membase + XI3C_INTR_STATUS_OFFSET),
		  master->membase + XI3C_INTR_STATUS_OFFSET);

	/* Reset fifos */
	xi3c_master_reset_fifos(master);

	/* Enable controller */
	xi3c_master_enable(master);
}

Since XI3C_INTR_RE_OFFSET is zeroed but the Hot-Join ACK bit might remain
active in XI3C_CR_OFFSET, could the controller silently ACK hot-join requests
without generating CPU interrupts, permanently stalling bus enumeration?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260909071340.3649271-1-shubhamsanjay.patil@amd.com?part=3