[PATCH 02/17] i3c: renesas: Use the divider 128

[Claudiu Beznea]

On 5/22/26 22:06, Frank Li wrote:
> On Fri, May 22, 2026 at 01:18:00PM +0300, Claudiu Beznea wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj at bp.renesas.com>
>>
>> The REFCKCTL.IREFCKS field is 3 bits wide, and setting it to 7 selects a
>> divider of 128 for the internal reference clock. Use this divider value.
> 
> This doesnot reflect what your change, code add one more search for clks = 7

cks is later written in the renesas_i3c_bus_init() to the REFCKCTL.IREFCKS. The 
following lines are from the renesas_i3c_bus_init() function:

	renesas_writel(i3c->regs, REFCKCTL, REFCKCTL_IREFCKS(cks));
	i3c->refclk_div = cks;

> 
> Frank
> 
>>
>> Fixes: d028219a9f14 ("i3c: master: Add basic driver for the Renesas I3C controller")
>> Cc: stable at vger.kernel.org
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj at bp.renesas.com>
>> ---
>>   drivers/i3c/master/renesas-i3c.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/i3c/master/renesas-i3c.c b/drivers/i3c/master/renesas-i3c.c
>> index 36e3ccbe66b0..1917549cf6d5 100644
>> --- a/drivers/i3c/master/renesas-i3c.c
>> +++ b/drivers/i3c/master/renesas-i3c.c
>> @@ -559,7 +559,7 @@ static int renesas_i3c_bus_init(struct i3c_master_controller *m)
>>
>>   	i2c_parse_fw_timings(&m->dev, &t, true);
>>
>> -	for (cks = 0; cks < 7; cks++) {
>> +	for (cks = 0; cks <= 7; cks++) {
>>   		/* SCL low-period calculation in Open-drain mode */
>>   		od_low_ticks = ((i2c_total_ticks * 6) / 10);
>>
>> --
>> 2.43.0
>>

-- 
Thank you,
Claudiu