[PATCH v4 07/12] i3c: dw-i3c-master: Add SETAASA as supported CCC

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Hardware registers are accessed before runtime PM is resumed, potentially causing a bus fault.
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commit 0dd3a1716725800c8f7459a7e2204416a4488acf
Author: Akhil R <akhilrajeev at nvidia.com>

i3c: dw-i3c-master: Add SETAASA as supported CCC

This commit adds SETAASA and SETHID to the supported list of CCC commands for
the DesignWare I3C host controller. SETAASA assigns predefined static
addresses to all devices on the bus, and SETHID stops HID bit flipping as a
prerequisite.

> diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
> index 971b429b76bc8..3e510fddf06c5 100644
> --- a/drivers/i3c/master/dw-i3c-master.c
> +++ b/drivers/i3c/master/dw-i3c-master.c
> @@ -309,6 +309,8 @@ static bool dw_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m,
>  	case I3C_CCC_GETSTATUS:
>  	case I3C_CCC_GETMXDS:
>  	case I3C_CCC_GETHDRCAP:
> +	case I3C_CCC_SETAASA:
> +	case I3C_CCC_VENDOR(0, true): /* SETHID */
>  		return true;
>  	default:
>  		return false;

[ ... ]

> static int dw_i3c_master_send_ccc_cmd(struct i3c_master_controller *m,
> 				      struct i3c_ccc_cmd *ccc)
> {
> 	struct dw_i3c_master *master = to_dw_i3c_master(m);
> 	int ret = 0;
> 
> 	if (ccc->id == I3C_CCC_ENTDAA)
> 		return -EINVAL;
> 
> 	/* AMD platform specific OD and PP timings */
> 	if (master->quirks & AMD_I3C_OD_PP_TIMING) {
> 		amd_configure_od_pp_quirk(master);
> 		writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING);
> 		writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING);
> 	}
> 
> 	ret = pm_runtime_resume_and_get(master->dev);

[Severity: High]
This is a pre-existing issue, but could accessing these hardware registers
before runtime PM is resumed cause a bus fault?

If the device is runtime-suspended, its clocks and power domains are disabled.
Accessing memory-mapped registers of a clock-gated device here might lead to
an asynchronous bus error or a system hang.

Should the register writes be moved after pm_runtime_resume_and_get()
completes successfully?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260616095429.3947205-1-akhilrajeev@nvidia.com?part=7