[PATCH v10 1/2] dt-bindings: i3c: Add AMD I3C master controller support

[Pandey, Radhey Shyam]

> From: Manikanta Guntupalli <manikanta.guntupalli at amd.com>
> 
> Add device tree binding documentation for the AMD I3C master controller
> version 1.0.
> 
> Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli at amd.com>
> Co-developed-by: Shubham Patil <shubhamsanjay.patil at amd.com>
> Signed-off-by: Shubham Patil <shubhamsanjay.patil at amd.com>
> Reviewed-by: Rob Herring (Arm) <robh at kernel.org>
> ---
v10 changes looks fine to me.

Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey at amd.com>
Thanks!

> Changes for V10:
> Use symbolic interrupt macros and include arm-gic.h.
> Added Shubham Patil as Co-developed-by / Signed-off-by on the binding.
> 
> Changes for V9:
> Updated the MAINTAINER section.
> 
> Changes for V8:
> None.
> 
> Changes for V7:
> Added i3c controller version details to commit description.
> 
> Changes for V6:
> Corrected the file name for $id in yaml to fix the dtschema warning.
> 
> Changes for V5:
> Renamed the xlnx,axi-i3c.yaml file into xlnx,axi-i3c-1.0.yaml.
> 
> Changes for V4:
> Added h/w documentation details.
> 
> Changes for V3:
> Updated commit description.
> Corrected the order of properties and removed resets property.
> Added compatible to required list.
> Added interrupts to example.
> 
> Changes for V2:
> Updated commit subject and description.
> Moved allOf to after required.
> Removed xlnx,num-targets property.
> ---
>   .../bindings/i3c/xlnx,axi-i3c-1.0.yaml        | 58 +++++++++++++++++++
>   1 file changed, 58 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/i3c/xlnx,axi-i3c-1.0.yaml
> 
> diff --git a/Documentation/devicetree/bindings/i3c/xlnx,axi-i3c-1.0.yaml b/Documentation/devicetree/bindings/i3c/xlnx,axi-i3c-1.0.yaml
> new file mode 100644
> index 000000000000..2caa245a8656
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/i3c/xlnx,axi-i3c-1.0.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/i3c/xlnx,axi-i3c-1.0.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: AMD I3C master
> +
> +maintainers:
> +  - Shubhrajyoti Datta <shubhrajyoti.datta at amd.com>
> +  - Shubham Patil <shubhamsanjay.patil at amd.com>
> +
> +description:
> +  The AXI-I3C IP is an I3C Controller with an AXI4-Lite interface, compatible
> +  with the MIPI I3C Specification v1.1.1. The design includes bidirectional I/O
> +  buffers that implement open collector drivers for the SDA and SCL signals.
> +  External pull-up resistors are required to properly hold the bus at a Logic-1
> +  level when the drivers are released.
> +
> +  For more details, please see https://docs.amd.com/r/en-US/pg439-axi-i3c
> +
> +properties:
> +  compatible:
> +    const: xlnx,axi-i3c-1.0
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +
> +allOf:
> +  - $ref: i3c.yaml#
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    i3c at 80000000 {
> +        compatible = "xlnx,axi-i3c-1.0";
> +        reg = <0x80000000 0x10000>;
> +        clocks = <&zynqmp_clk 71>;
> +        interrupt-parent = <&imux>;
> +        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> +        #address-cells = <3>;
> +        #size-cells = <0>;
> +    };
> +...