[PATCH V8 4/5] i3c: master: Add endianness support for i3c_readl_fifo() and i3c_writel_fifo()

[Frank Li]

On Fri, Sep 26, 2025 at 01:09:37PM +0200, Arnd Bergmann wrote:
> On Fri, Sep 26, 2025, at 12:53, Manikanta Guntupalli wrote:
> > Add endianness handling to the FIFO access helpers i3c_readl_fifo() and
> > i3c_writel_fifo(). This ensures correct data transfers on platforms where
> > the FIFO registers are expected to be accessed in either big-endian or
> > little-endian format.
> >
> > Update the Synopsys, Cadence, and Renesas I3C master controller drivers to
> > pass the appropriate endianness argument to these helpers.
> >
> > Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli at amd.com>
> > Reviewed-by: Frank Li <Frank.Li at nxp.com>
>
> I don't think this is a good interface, based on our discussion
> so far, and I had hoped you'd change it the way I had suggested
> with a separate function for the xi3c driver, so normal drivers
> don't have to worry about the AMD specific quirk.
>
> I think this should also avoid mentioning "endianess" in the
> changelog and in the code itself, since that would likely
> confuse readers into thinking (as I did in my earlier replies)
> that this is related to using big-endian kernels.
>
> i3c_readl_fifo()/i3c_writel_fifo() are already portable and
> handle endianess correctly by using the readsl()/writesl()
> functions.

I agree. I think previous your suggested API is good.

/*
 * BIT: 31..24   23..16  15..8   7..0
 *       B0       B1       B2    B3
 *
 * Memory:
 *  0x0:  B0
 *  0x1:  B1
 *  0x2:  B2
 *  0x3:  B3
 */
i3c_writel_fifo_bytereversed()


Frank
>
>     Arnd
>
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