[PATCH V7 3/4] i3c: master: Add endianness support for i3c_readl_fifo() and i3c_writel_fifo()

[Guntupalli, Manikanta]

[Public]

Hi,

> -----Original Message-----
> From: Arnd Bergmann <arnd at arndb.de>
> Sent: Wednesday, September 24, 2025 9:13 PM
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> Cc: Pandey, Radhey Shyam <radhey.shyam.pandey at amd.com>; Goud, Srinivas
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> Subject: Re: [PATCH V7 3/4] i3c: master: Add endianness support for i3c_readl_fifo()
> and i3c_writel_fifo()
>
> On Wed, Sep 24, 2025, at 17:23, Guntupalli, Manikanta wrote:
> >> Subject: Re: [PATCH V7 3/4] i3c: master: Add endianness support for
> >> i3c_readl_fifo() and i3c_writel_fifo()
> >> > }
> >> >
> >> > With this approach, both little-endian and big-endian cases works as expected.
> >>
> >> This version should fix the cases where you have a big-endian kernel
> >> with either I3C_FIFO_BIG_ENDIAN or I3C_FIFO_LITTLE_ENDIAN, as neither
> >> combination does any byte swaps.
> >>
> >> However I'm fairly sure it's still broken for little-endian kernels
> >> when a driver asks for a I3C_FIFO_BIG_ENDIAN conversion, same as v7.
> > We tested using the I3C_FIFO_BIG_ENDIAN flag from the driver on
> > little-endian kernels, and it works as expected.
>
> Can you explain how that works? What I see is that your
> readsl_be()/writesl_be() functions do a byteswap on every four bytes, so the
> bytestream that gets copied to/from the FIFO gets garbled, in particular the final
> (unaligned) bytes of the kernel buffer end up in the higher bytes of the FIFO register
> rather than the first bytes as they do on a big-endian kernel.
>
> Are both the big-endian and little-endian kernels in your tests on microblaze, using
> the upstream version of asm/io.h? Is there a hardware byteswap between the CPU
> local bus and the i3c controller? If there is one, is it set the same way for both
> kernels?
>
To clarify, my testing was performed on the latest upstream kernel on a ZCU102 (Zynq UltraScale+ MPSoC, Cortex-A53, little-endian) with big-endian FIFOs and no bus-level byteswap. For more details, please refer to my reply in Re: [PATCH] [v2] i3c: fix big-endian FIFO transfers.

Please don't take this as negative or aggressive-my intention is purely to learn and ensure it works correctly in all cases.

Thanks,
Manikanta.