[PATCH v3 2/3] arm64: dts: intel: agilex5: Add Altera compatible for I3C controllers

[Frank Li]

On Fri, Oct 31, 2025 at 05:05:57PM +0800, adrianhoyin.ng at altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng at altera.com>
>
> Add the "altr,agilex5-dw-i3c-master" compatible string to the
> I3C controller nodes on the Agilex5 SoCFPGA platform.

Suppose this should be enough. the below context is common sense.

> This allows
> the platform to use the generic Synopsys DW I3C master driver while
> enabling platform-specific quirks or configurations associated with
> Altera SoCFPGA devices.
>
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng at altera.com>
> ---
>  arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 04e99cd7e74b..c494b3bbb5e9 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -203,7 +203,8 @@ i2c4: i2c at 10c02c00 {
>  		};
>
>  		i3c0: i3c at 10da0000 {
> -			compatible = "snps,dw-i3c-master-1.00a";
> +			compatible = "altr,agilex5-dw-i3c-master",
> +						"snps,dw-i3c-master-1.00a";

Need align to previous line

Frank

>  			reg = <0x10da0000 0x1000>;
>  			#address-cells = <3>;
>  			#size-cells = <0>;
> @@ -213,7 +214,8 @@ i3c0: i3c at 10da0000 {
>  		};
>
>  		i3c1: i3c at 10da1000 {
> -			compatible = "snps,dw-i3c-master-1.00a";
> +			compatible = "altr,agilex5-dw-i3c-master",
> +						"snps,dw-i3c-master-1.00a";
>  			reg = <0x10da1000 0x1000>;
>  			#address-cells = <3>;
>  			#size-cells = <0>;
> --
> 2.49.GIT
>