[PATCH v6 3/5] i3c: master: svc: Add basic HDR mode support

[Frank Li]

On Thu, Oct 23, 2025 at 11:29:53AM +0300, Andy Shevchenko wrote:
> On Tue, Oct 14, 2025 at 12:40:02PM -0400, Frank Li wrote:
> > Add basic HDR mode support for the svs I3C master driver.
> >
> > Only support for private transfers and does not support sending CCC
> > commands in HDR mode.
> >
> > Key differences:
> > - HDR uses commands (0x00-0x7F for write, 0x80-0xFF for read) to
> > distinguish transfer direction.
> > - HDR read/write commands must be written to FIFO before issuing the I3C
> > address command. The hardware automatically sends the standard CCC command
> > to enter HDR mode.
> > - HDR exit pattern must be sent instead of send a stop after transfer
> > completion.
> > - Read/write data size must be an even number.
>
> ...
>
> > +static void svc_i3c_master_emit_force_exit(struct svc_i3c_master *master)
> > +{
> > +	u32 reg = 0;
>
> Useless.
>
> > +	writel(SVC_I3C_MCTRL_REQUEST_FORCE_EXIT, master->regs + SVC_I3C_MCTRL);
> > +	readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
> > +			   SVC_I3C_MSTATUS_MCTRLDONE(reg), 0, 1000);
>
> No error checks? Why is it okay?
> Why is the first parameter 0 while it's not an _atomic() call?
>
> > +	udelay(1);
>
> No explanations given. Also is it really need to be atomic? If not, use
> fsleep() and it will choose the best suitable API under the hood.

It is in atomic context. I will add comments.

Frank

>
> >  }
>
> ...
>
> > +	if (xfer_type == SVC_I3C_MCTRL_TYPE_DDR) {
> > +		/* DDR command need prefill into FIFO */
> > +		writel(rnw_cmd, master->regs + SVC_I3C_MWDATAB);
> > +		if (!rnw) {
> > +			/* write data also need prefill into FIFO */
> > +			ret = svc_i3c_master_write(master, out, xfer_len);
> > +		if (ret)
> > +			goto emit_stop;
> > +		}
>
> The indentation here is a mess.
>
> > +	}
>
> --
> With Best Regards,
> Andy Shevchenko
>
>