[PATCH v9 4/6] i3c: master: svc: Add basic HDR mode support

[Andy Shevchenko]

On Fri, Oct 31, 2025 at 12:39:16PM -0400, Frank Li wrote:
> Add basic HDR mode support for the svs I3C master driver.
> 
> Only support for private transfers and does not support sending CCC
> commands in HDR mode.
> 
> Key differences:
> - HDR uses commands (0x00-0x7F for write, 0x80-0xFF for read) to
> distinguish transfer direction.
> - HDR read/write commands must be written to FIFO before issuing the I3C
> address command. The hardware automatically sends the standard CCC command
> to enter HDR mode.
> - HDR exit pattern must be sent instead of send a stop after transfer
> completion.
> - Read/write data size must be an even number.

...

>  static bool svc_cmd_is_read(u32 rnw_cmd, u32 type)
>  {
> -	return rnw_cmd;
> +	return (type == SVC_I3C_MCTRL_TYPE_DDR) ? !!(rnw_cmd & 0x80) : rnw_cmd;

This seems confusing. Either !! is redundant (which is actually the case) or
I don't know what the idea behind this.

> +}

...

> +static void svc_i3c_master_emit_force_exit(struct svc_i3c_master *master)
> +{
> +	u32 reg;
> +
> +	writel(SVC_I3C_MCTRL_REQUEST_FORCE_EXIT, master->regs + SVC_I3C_MCTRL);
> +
> +	/*
> +	 * Not need check error here because it is never happen at hardware. IP

If you move 'IP' to the next line it will be better to read.

> +	 * just wait for few fclk cycle to complete DDR exit pattern. Even
> +	 * though fclk stop, timeout happen here, the whole data actually
> +	 * already finish transfer. The next command will be timeout because
> +	 * wrong hardware state.
> +	 */
> +	readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, reg,
> +				  SVC_I3C_MSTATUS_MCTRLDONE(reg), 0, 1000);
> +
> +	/*
> +	 * This delay is necessary after the emission of a stop, otherwise eg.
> +	 * repeating IBIs do not get detected. There is a note in the manual
> +	 * about it, stating that the stop condition might not be settled
> +	 * correctly if a start condition follows too rapidly.
> +	 */
> +	udelay(1);
>  }

-- 
With Best Regards,
Andy Shevchenko