[PATCH v2 3/4] i3c: mipi-i3c-hci: Change name of INTR_STATUS bit 11

[Frank Li]

On Wed, Mar 12, 2025 at 01:10:48PM +0200, Jarkko Nikula wrote:
> INTR_STATUS bit 11 INTR_HC_RESET_CANCEL was probably projected for the
> MIPI I3C HCI specification version 2 but was not ever implemented.
>
> This bit is first time specified in the v1.2 as HC_SEQ_CANCEL_STAT
> "Host Controller Cancelled Transaction Sequence". Update the definition
> and debug print of it accordingly.
>
> While at it, change DBG() print to dev_dbg().
>

Reviewed-by: Frank Li <Frank.Li at nxp.com>

> Signed-off-by: Jarkko Nikula <jarkko.nikula at linux.intel.com>
> ---
>  drivers/i3c/master/mipi-i3c-hci/core.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
> index e5593b6e897e..84c372740020 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
> @@ -78,7 +78,7 @@
>  #define INTR_SIGNAL_ENABLE		0x28
>  #define INTR_FORCE			0x2c
>  #define INTR_HC_CMD_SEQ_UFLOW_STAT	BIT(12)	/* Cmd Sequence Underflow */
> -#define INTR_HC_RESET_CANCEL		BIT(11)	/* HC Cancelled Reset */
> +#define INTR_HC_SEQ_CANCEL		BIT(11)	/* HC Cancelled Transaction Sequence */
>  #define INTR_HC_INTERNAL_ERR		BIT(10)	/* HC Internal Error */
>
>  #define DAT_SECTION			0x30	/* Device Address Table */
> @@ -597,9 +597,10 @@ static irqreturn_t i3c_hci_irq_handler(int irq, void *dev_id)
>  		result = IRQ_HANDLED;
>  	}
>
> -	if (val & INTR_HC_RESET_CANCEL) {
> -		DBG("cancelled reset");
> -		val &= ~INTR_HC_RESET_CANCEL;
> +	if (val & INTR_HC_SEQ_CANCEL) {
> +		dev_dbg(&hci->master.dev,
> +			"Host Controller Cancelled Transaction Sequence\n");
> +		val &= ~INTR_HC_SEQ_CANCEL;
>  	}
>  	if (val & INTR_HC_INTERNAL_ERR) {
>  		dev_err(&hci->master.dev, "Host Controller Internal Error\n");
> --
> 2.47.2
>
>
> --
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