[PATCH 1/4] i3c: mipi-i3c-hci: Allow only relevant INTR_STATUS bit updates

[Frank Li]

On Fri, Feb 28, 2025 at 04:17:59PM +0200, Jarkko Nikula wrote:
> Since MIPI I3C HCI specification version v0.8 INTR_STATUS bits 9:0 are
> reserved. Version v0.5 has bits 9 and 5:0 in use but not handled by the
> current driver code and not needed in DMA transfers.
>
> PIO transfers with v0.5 would require changes to both
> core.c: i3c_hci_irq_handler() and pio.c: hci_pio_irq_handler() though.

If reasonable, why not change core.c and pio.c?

>
> For these reasons don't enable signal updates from INTR_STATUS bits 9:0.
>
> This change is a no-op for specification versions v0.8 and beyond but
> gets rid of "unexpected INTR_STATUS" errors if somebody (read me) wants
> to run code on old v0.5 IP version.

I think, simple said
"Get rid of "unexpected INTR_STATUS" errors at old v0.5 IP version and
no-op for version above v0.8."

>
> Signed-off-by: Jarkko Nikula <jarkko.nikula at linux.intel.com>
> ---
>  drivers/i3c/master/mipi-i3c-hci/core.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
> index a71226d7ca59..e139d7e4d252 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
> @@ -699,9 +699,10 @@ static int i3c_hci_init(struct i3c_hci *hci)
>  	if (ret)
>  		return -ENXIO;
>
> -	/* Disable all interrupts and allow all signal updates */
> +	/* Disable all interrupts */
>  	reg_write(INTR_SIGNAL_ENABLE, 0x0);
> -	reg_write(INTR_STATUS_ENABLE, 0xffffffff);
> +	/* Allow signal updates relevant to IP versions 0.8 and beyond */
> +	reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10));

Generally, just enable needed IRQ in driver. Define some BITS for
difference type IRQs.

Frank

>
>  	/* Make sure our data ordering fits the host's */
>  	regval = reg_read(HC_CONTROL);
> --
> 2.47.2
>
>
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