Query regarding Linux Arm pagetable setup

[Catalin Marinas]

On Thu, May 05, 2016 at 04:17:08PM +0530, Dushyant Behl wrote:
> I am looking at the kernel 4.1.0 execution with Arm-v7 architecture
> and LPAE enabled.
> 
> I am not able to understand what is the use of TTBR1 page table mappings.
> The settings in TTBCR register are T0SZ - 0 and T1SZ - 2, which indicate a
> 3G-1G split but if I look at the TTBR1 page table then it doesn't
> contains some of the actual required high address (1G range) mappings
> while they are present in the TTBR0 page table.
> 
> Can someone explain how the kernel is using both the TTBR0 and TTBR1
> and how some mappings which should've been present in TTBR1 are
> actually used through the TTBR0 register?

With the 3-1 split, TTBR1 only needs to cover 1GB of virtual memory.
This means that Level 1 page table is disabled (pgd/pud) and the first 3
pmd pages are also skipped. The architecture does not allow TTBRx sizes
with a single entry at the top level, meaning that the number of levels
must be reduced.

To recap: with LPAE, 1 pgd/pud entry covers 1GB of VA, the same as a
full pmd page (4K/8 entries * 2MB per entry). So for 1GB kernel mapping
in TTBR1 we only need 512 pmd entries == 1 4KB page for the pmd. The
v7_ttb_setup macro in arch/arm/mm/proc-v7-3level.S adjusts the TTBR1
value (initially pointing at swapper_pg_dir) with TTBR1_OFFSET (defined
in pgtable-3level-hwdef.h).

So I think you may just be mis-reading the page table pointed at by
TTBR1.

-- 
Catalin