set_fiq_handler: Bad mode in data abort handler detected

[Tim Sander]

Hi

I have installed a FIQ handler with set_fiq_handler on an Xilinx Zynq. 
I had to enable the the FIQ symbol in kconfig for the Zynq as its not enabled
by default. As i was not able to boot a mainline kernel i used the 3.12 kernel
of the xilinx repository at github. But as there are no changes in the FIQ handler
stuff i guess that does not matter. The Zynq is a dual ArmV7 Cortex A9.
The handler works for an random timespan and then i see:

Bad mode in data abort handler detected
Internal error: Oops - bad mode: 0 [#1] PREEMPT SMP ARM
Modules linked in: firq(O) ipv6
CPU: 0 PID: 0 Comm: swapper/0 Tainted: G           O 3.12.0-xilinx-dirty #54
task: c05bd420 ti: c05b2000 task.ti: c05b2000
PC is at 0xffff1224
LR is at arch_cpu_idle+0x20/0x2c
pc : [<ffff1224>]    lr : [<c000f344>]    psr: 600e01d1
sp : c05b3f70  ip : 00000000  fp : 00000000
r10: 00000000  r9 : 413fc090  r8 : c0a264c0
r7 : c05a7720  r6 : c04080c8  r5 : c05f2500  r4 : c05b2000
r3 : 00000000  r2 : 00000000  r1 : 00000000  r0 : c0a299f8
Flags: nZCv  IRQs off  FIQs off  Mode FIQ_32  ISA ARM  Segment kernel
Control: 18c5387d  Table: 1ec0404a  DAC: 00000015
Process swapper/0 (pid: 0, stack limit = 0xc05b2240)
Stack: (0xc05b3f70 to 0xc05b4000)
3f60:                                     c0a299f8 00000000 00000000 00000000
3f80: c05b2000 c05f2500 c04080c8 c05a7720 c0a264c0 413fc090 00000000 00000000
3fa0: 00000000 c05b3f70 c000f344 ffff1224 600e01d1 ffffffff 00000000 c0055fb8
3fc0: c040a7b0 c0584a5c ffffffff ffffffff c0584574 00000000 00000000 c05a7720
3fe0: 18c5387d c05ba3cc c05a771c c05be440 0000406a 00008074 00000000 00000000
[<c000f344>] (arch_cpu_idle+0x20/0x2c) from [<00000000>] (  (null))
Code: e320f000 e320f000 e320f000 eafffffe (e5889000) 
---[ end trace e6db5c17f3b781c3 ]---
Kernel panic - not syncing: Attempted to kill the idle task!
CPU1: stopping
CPU: 1 PID: 0 Comm: swapper/1 Tainted: G      D    O 3.12.0-xilinx-dirty #54
[<c0015568>] (unwind_backtrace+0x0/0x11c) from [<c00117e4>] (show_stack+0x10/0x14)
[<c00117e4>] (show_stack+0x10/0x14) from [<c0400b90>] (dump_stack+0x7c/0xc0)
[<c0400b90>] (dump_stack+0x7c/0xc0) from [<c0013e0c>] (ipi_cpu_stop+0x3c/0x6c)
[<c0013e0c>] (ipi_cpu_stop+0x3c/0x6c) from [<c0014418>] (handle_IPI+0x60/0xa4)
[<c0014418>] (handle_IPI+0x60/0xa4) from [<c00084e0>] (gic_handle_irq+0x58/0x60)
[<c00084e0>] (gic_handle_irq+0x58/0x60) from [<c0012280>] (__irq_svc+0x40/0x70)
Exception stack(0xdf485fa0 to 0xdf485fe8)
5fa0: c0a319f8 00000000 00000000 00000000 df484000 00000015 c04080c8 c05f2820
5fc0: 0000406a 413fc090 00000000 00000000 00000000 df485fe8 c000f344 c000f348
5fe0: 60070013 ffffffff
[<c0012280>] (__irq_svc+0x40/0x70) from [<c000f348>] (arch_cpu_idle+0x24/0x2c)
[<c000f348>] (arch_cpu_idle+0x24/0x2c) from [<c0055fb8>] (cpu_startup_entry+0xb4/0x118)
[<c0055fb8>] (cpu_startup_entry+0xb4/0x118) from [<00008584>] (0x8584)

My first guess would be that i had a cache page miss in the fiq handler? I guess the best way would
be putting the fiq-handler on the On Chip Memory but then i would still have the same problem that
the code jumping to the OCM would have a cache miss?

The fiq code uses r8 for the time base, r9 as reset value for the timer generating the interrupt
and r10 as base address for some mmaped LEDs:
    str     r9, [r8]                               /* reset timer */                 
    str     fp, [sl]                                /* set leds*/
    add     fp, fp, #1                         /* increment led counter */
    subs    pc, lr, #4                         /* return from fiq */

Best regards
Tim