From f7e85ef14c52e84e495ab85fd07263e5b909bf7f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 27 Feb 2022 02:20:05 +0100 Subject: [PATCH] arm64: dts: imx8mp: Add display pipeline components MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add DSIM, DSIM PHY, LCDIF1 and mediamix blk_ctl nodes for iMX8MP. The blk_ctl is required to enable LCDIF clock and DSIM clock, and handle DSIM resets. Upstream-Status: Pending Signed-off-by: Marek Vasut Cc: Abel Vesa Cc: Dong Aisheng Cc: Fabio Estevam Cc: Guido Günther Cc: Lucas Stach Cc: NXP Linux Team Cc: Rob Herring Cc: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 144 +++++++++++++++++++++- 1 file changed, 139 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index bb916a0948a8f..aef39d62b47d7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -533,6 +533,7 @@ pgc { pgc_mipi_phy1: power-domain@0 { #power-domain-cells = <0>; reg = ; + power-domains = <&pgc_mediamix>; }; pgc_pcie_phy: power-domain@1 { @@ -587,6 +588,7 @@ pgc_mediamix: power-domain@10 { pgc_mipi_phy2: power-domain@16 { #power-domain-cells = <0>; reg = ; + power-domains = <&pgc_mediamix>; }; pgc_hsiomix: power-domains@17 { @@ -1082,7 +1084,7 @@ aips4: bus@32c00000 { media_blk_ctrl: blk-ctrl@32ec0000 { compatible = "fsl,imx8mp-media-blk-ctrl", - "syscon"; + "simple-bus", "syscon"; reg = <0x32ec0000 0x10000>; power-domains = <&pgc_mediamix>, <&pgc_mipi_phy1>, @@ -1120,14 +1122,146 @@ media_blk_ctrl: blk-ctrl@32ec0000 { <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2", "isp", "phy"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_VIDEO_PLL1_OUT>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_VIDEO_PLL1_OUT>; + assigned-clock-rates = <0>, <0>, <594000000>; + + #power-domain-cells = <1>; - assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + lvds_ldb: lvds-ldb { + #address-cells = <0>; + #size-cells = <0>; + compatible = "fsl,imx8mp-ldb"; + clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; + clock-names = "ldb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + ldb_from_lcdif2: endpoint { + remote-endpoint = <&lcdif2_to_ldb>; + }; + }; + + /* LVDS single-link or dual-link */ + port@1 { + reg = <1>; + + ldb_lvds_ch0: endpoint { + }; + }; + + port@2 { + reg = <2>; + + ldb_lvds_ch1: endpoint { + }; + }; + }; + }; + }; + + mipi_dsi: mipi_dsi@32e60000 { + #address-cells = <0>; + #size-cells = <0>; + compatible = "fsl,imx8mp-mipi-dsim"; + reg = <0x32e60000 0x400>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + clock-names = "bus_clk", "sclk_mipi"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <266000000>, <24000000>; + samsung,pll-clock-frequency = <24000000>; + interrupts = ; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>; + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + dsim_from_lcdif1: endpoint { + remote-endpoint = <&lcdif1_to_dsim>; + }; + }; + }; + }; + + lcdif1: display-controller@32e80000 { + #address-cells = <0>; + #size-cells = <0>; + compatible = "fsl,imx8mp-lcdif"; + reg = <0x32e80000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "pix", "disp_axi", "axi"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI>, <&clk IMX8MP_CLK_MEDIA_APB>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + assigned-clock-parents = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <500000000>, <200000000>; + assigned-clock-rates = <594000000>, <500000000>, <200000000>; + interrupts = ; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>; + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; - #power-domain-cells = <1>; + lcdif1_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif1>; + }; + }; + }; + }; + + lcdif2: display-controller@32e90000 { + #address-cells = <0>; + #size-cells = <0>; + compatible = "fsl,imx8mp-lcdif"; + reg = <0x32e90000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "pix", "disp_axi", "axi"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <594000000>, <500000000>, <200000000>; + interrupts = ; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + lcdif2_to_ldb: endpoint { + remote-endpoint = <&ldb_from_lcdif2>; + }; + }; + }; }; pcie_phy: pcie-phy@32f00000 { -- 2.39.0