#define SYS_clkgen0_pll     0x10000
#define SYS_cpuclk_div_ctrl 0x10024
#define TANGOX_XTAL_FREQ 27000

#define REG(name, ...) union name { struct { u32 __VA_ARGS__; } f; u32 val; }

REG(SYS_clkgen_pll, N:7, :6, K:3, M:3, :5, Isel:3, :3, T:1, B:1);
REG(SYS_clk_div_ctrl, F:4, :4, I:8, :4, RS:1, RE:2, BP:1, :7, BZ:1);

#define SYS_FAST_RAMP 1
#define SYS_FAST_RAMP_SPEED 15 /* in kHz per nanosecond */
#define SYS_CLK_DIV_CTRL(DI) {{ .I = DI, .RE = SYS_FAST_RAMP }}