>From 5ba960969738091f5e0e9bd18090df7e64c39ace Mon Sep 17 00:00:00 2001
From: Sylvain Rochet <sylvain.rochet@finsecur.com>
Date: Thu, 18 Dec 2014 20:11:48 +0100
Subject: [PATCH] AT91/PM: slow clock mode fixes

---
 arch/arm/mach-at91/pm_slowclock.S | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 6194749..9cad710 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -33,11 +33,11 @@
  */
 #undef SLOWDOWN_MASTER_CLOCK
 
-#define MCKRDY_TIMEOUT		1000
+#define MCKRDY_TIMEOUT		4000
 #define MOSCRDY_TIMEOUT 	1000
 #define PLLALOCK_TIMEOUT	1000
-#define PLLBLOCK_TIMEOUT	1000
-#define UPLLLOCK_TIMEOUT	1000
+#define PLLBLOCK_TIMEOUT	15000000
+#define UPLLLOCK_TIMEOUT	15000000
 
 pmc	.req	r0
 sdramc	.req	r1
@@ -94,7 +94,7 @@ flag	.req	r7
  * Wait until PLLB has locked.
  */
 	.macro wait_pllblock
-	mov	tmp2, #PLLBLOCK_TIMEOUT
+	ldr	tmp2, .pllblock_timeout
 1:	sub	tmp2, tmp2, #1
 	cmp	tmp2, #0
 	beq	2f
@@ -108,7 +108,7 @@ flag	.req	r7
  * Wait until UTMI PLL has locked.
  */
 	.macro wait_uplllock
-	mov	tmp2, #UPLLLOCK_TIMEOUT
+	ldr	tmp2, .uplllock_timeout
 1:	sub	tmp2, tmp2, #1
 	cmp	tmp2, #0
 	beq	2f
@@ -340,13 +340,13 @@ sdr_sr_done:
 
 	/* Turn on UTMI PLL */
 	cmp	flag, #1
-	bne	1f
+	bne	3f
 	ldr	tmp1, [pmc, #AT91_CKGR_UCKR]
 	orr	tmp1, tmp1, #AT91_PMC_UPLLEN
 	str	tmp1, [pmc, #AT91_CKGR_UCKR]
 
 	wait_uplllock
-1:
+3:
 
 	/* Restore PLLB setting */
 	ldr	tmp1, .saved_pllbr
@@ -430,5 +430,11 @@ ram_restored:
 .saved_sam9_lpr1:
 	.word 0
 
+.pllblock_timeout:
+	.word PLLBLOCK_TIMEOUT
+
+.uplllock_timeout:
+	.word UPLLLOCK_TIMEOUT
+
 ENTRY(at91_slow_clock_sz)
 	.word .-at91_slow_clock
-- 
2.1.3