<p>Hi~<br></p>
<p>This code should be changed.</p>
<p>I insert this code (save/restore clock source register - CLK_SRC_TOP3) temporary.</p>
<p>But we removed this code. And we use another method to fix it.<br></p>
<p>I think this is not right way.<br></p>
<p>Thanks.</p>
<p> <br><br></p>
<div class="gmail_quote">On Fri, Dec 21, 2012 at 6:06 AM, <span dir="ltr"><<a href="mailto:tomasz.figa@gmail.com" target="_blank">tomasz.figa@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Hi Prasanna,<br>
<div><br>
On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:<br>
> This patch adds a software workaround to the hardware<br>
> problem found in exynos5 while powergating.<br>
><br>
> It is observed that CLK_TOP_SRC3 register gets modified if<br>
> the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets<br>
> set to XXTI which results in the device running very slow .<br>
> A big drop in performance is noticed whilerunning the video.<br>
> This issue also occurs while powergating MFC.<br>
><br>
> The value of clock source register is restored once the powergating<br>
> operation is completed.<br>
<br>
</div>Is the problem really related to power gating at all? From what you<br>
described in comment in the code, it seems like it's a problem with<br>
suspend/resume, not power gating, so it should be rather saved on suspend<br>
and restored on resume. Please recheck clock save/restore part of power<br>
management code.<br>
<br>
Altering clock configuration registers from power domain code looks really<br>
ugly...<br>
<br>
Best regards,<br>
Tomasz Figa<br>
<div><div><br>
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