<div class="gmail_quote">2012/8/18 Belisko Marek <span dir="ltr"><<a href="mailto:marek.belisko@gmail.com" target="_blank">marek.belisko@gmail.com</a>></span><br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="HOEnZb"><div class="h5">On Sat, Aug 18, 2012 at 12:55 PM, Kelvin Cheung <<a href="mailto:keguang.zhang@gmail.com">keguang.zhang@gmail.com</a>> wrote:<br>
> This adds clock support to Loongson1B SoC using the common clock<br>
> infrastructure.<br>
><br>
> Signed-off-by: Kelvin Cheung <<a href="mailto:keguang.zhang@gmail.com">keguang.zhang@gmail.com</a>><br>
> ---<br>
> drivers/clk/Makefile | 1 +<br>
> drivers/clk/clk-ls1x.c | 108 ++++++++++++++++++++++++++++++++++++++++++++++++<br>
> 2 files changed, 109 insertions(+), 0 deletions(-)<br>
> create mode 100644 drivers/clk/clk-ls1x.c<br>
><br>
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile<br>
> index 5869ea3..018ec57 100644<br>
> --- a/drivers/clk/Makefile<br>
> +++ b/drivers/clk/Makefile<br>
> @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/<br>
> obj-$(CONFIG_PLAT_SPEAR) += spear/<br>
> obj-$(CONFIG_ARCH_U300) += clk-u300.o<br>
> obj-$(CONFIG_ARCH_INTEGRATOR) += versatile/<br>
> +obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o<br>
><br>
> # Chip specific<br>
> obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o<br>
> diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c<br>
> new file mode 100644<br>
> index 0000000..0aadf9d<br>
> --- /dev/null<br>
> +++ b/drivers/clk/clk-ls1x.c<br>
> @@ -0,0 +1,108 @@<br>
> +/*<br>
> + * Copyright (c) 2012 Zhang, Keguang <<a href="mailto:keguang.zhang@gmail.com">keguang.zhang@gmail.com</a>><br>
> + *<br>
> + * This program is free software; you can redistribute it and/or modify it<br>
> + * under the terms of the GNU General Public License as published by the<br>
> + * Free Software Foundation; either version 2 of the License, or (at your<br>
> + * option) any later version.<br>
> + */<br>
> +<br>
> +#include <linux/clkdev.h><br>
> +#include <linux/clk-provider.h><br>
> +#include <linux/io.h><br>
> +#include <linux/slab.h><br>
> +#include <linux/err.h><br>
> +#include <asm/mach-loongson1/loongson1.h><br>
> +<br>
> +#include <loongson1.h><br>
> +<br>
> +#define OSC 33<br>
> +<br>
> +static DEFINE_SPINLOCK(_lock);<br>
> +<br>
> +int ls1x_pll_clk_enable(struct clk_hw *hw)<br>
</div></div>^^^^static<br></blockquote><div><br>OK, will do.<br>Thanks!<br> </div><blockquote class="gmail_quote" style="margin:0pt 0pt 0pt 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<div class="im">> +{<br>
> + return 0;<br>
> +}<br>
> +<br>
> +void ls1x_pll_clk_disable(struct clk_hw *hw)<br>
</div>^^^^ also static<br>
<div><div class="h5">> +{<br>
> +}<br>
> +<br>
> +static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,<br>
> + unsigned long parent_rate)<br>
> +{<br>
> + u32 pll, rate;<br>
> +<br>
> + pll = __raw_readl(LS1X_CLK_PLL_FREQ);<br>
> + rate = ((12 + (pll & 0x3f)) * 1000000) +<br>
> + ((((pll >> 8) & 0x3ff) * 1000000) >> 10);<br>
> + rate *= OSC;<br>
> + rate >>= 1;<br>
> +<br>
> + return rate;<br>
> +}<br>
> +<br>
> +static const struct clk_ops ls1x_pll_clk_ops = {<br>
> + .enable = ls1x_pll_clk_enable,<br>
> + .disable = ls1x_pll_clk_disable,<br>
> + .recalc_rate = ls1x_pll_recalc_rate,<br>
> +};<br>
> +<br>
> +static struct clk * __init clk_register_pll(struct device *dev,<br>
> + const char *name, const char *parent_name, unsigned long flags)<br>
> +{<br>
> + struct clk_hw *hw;<br>
> + struct clk *clk;<br>
> + struct clk_init_data init;<br>
> +<br>
> + /* allocate the divider */<br>
> + hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);<br>
> + if (!hw) {<br>
> + pr_err("%s: could not allocate clk_hw\n", __func__);<br>
> + return ERR_PTR(-ENOMEM);<br>
> + }<br>
> +<br>
> + <a href="http://init.name" target="_blank">init.name</a> = name;<br>
> + init.ops = &ls1x_pll_clk_ops;<br>
> + init.flags = flags | CLK_IS_BASIC;<br>
> + init.parent_names = (parent_name ? &parent_name : NULL);<br>
> + init.num_parents = (parent_name ? 1 : 0);<br>
> + hw->init = &init;<br>
> +<br>
> + /* register the clock */<br>
> + clk = clk_register(dev, hw);<br>
> +<br>
> + if (IS_ERR(clk))<br>
> + kfree(hw);<br>
> +<br>
> + return clk;<br>
> +}<br>
> +<br>
> +void __init ls1x_clk_init(void)<br>
> +{<br>
> + struct clk *clk;<br>
> +<br>
> + clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT);<br>
> + clk_prepare_enable(clk);<br>
> +<br>
> + clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",<br>
> + CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,<br>
> + DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);<br>
> + clk_prepare_enable(clk);<br>
> + clk_register_clkdev(clk, "cpu", NULL);<br>
> +<br>
> + clk = clk_register_divider(NULL, "ddr_clk", "pll_clk",<br>
> + CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,<br>
> + DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);<br>
> + clk_prepare_enable(clk);<br>
> + clk_register_clkdev(clk, "ddr", NULL);<br>
> + clk_register_clkdev(clk, "stmmaceth", NULL);<br>
> +<br>
> + clk = clk_register_divider(NULL, "dc_clk", "pll_clk",<br>
> + CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,<br>
> + DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);<br>
> + clk_prepare_enable(clk);<br>
> + clk_register_clkdev(clk, "dc", NULL);<br>
> + clk_register_clkdev(clk, "serial8250", NULL);<br>
> +}<br>
> --<br>
> 1.7.1<br>
><br>
</div></div>> --<br>
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<br>
cheers,<br>
<br>
marek<br>
<span class="HOEnZb"><font color="#888888"><br>
--<br>
as simple and primitive as possible<br>
-------------------------------------------------<br>
Marek Belisko - OPEN-NANDRA<br>
Freelance Developer<br>
<br>
Ruska Nova Ves 219 | Presov, 08005 Slovak Republic<br>
Tel: +421 915 052 184<br>
skype: marekwhite<br>
twitter: #opennandra<br>
web: <a href="http://open-nandra.com" target="_blank">http://open-nandra.com</a><br>
</font></span></blockquote></div><br><br clear="all"><br>-- <br>Best Regards!<br>Kelvin<br><br><img src="http://ubuntucounter.geekosophical.net/img/ubuntu-blogger.php?user=26540"><br><br>