Adding Marek.<br><br>
<div class="gmail_quote">On Mon, Jul 30, 2012 at 2:15 PM, Leela Krishna Amudala <span dir="ltr"><<a href="mailto:l.krishna@samsung.com" target="_blank">l.krishna@samsung.com</a>></span> wrote:<br>
<blockquote style="BORDER-LEFT:#ccc 1px solid;MARGIN:0px 0px 0px 0.8ex;PADDING-LEFT:1ex" class="gmail_quote">Moved the contents of regs-fb-v4.h and regs-fb.h from arch side<br>to include/video/samsung_fimd.h<br><br>Signed-off-by: Leela Krishna Amudala <<a href="mailto:l.krishna@samsung.com">l.krishna@samsung.com</a>><br>
---<br> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 159 -------<br> arch/arm/plat-samsung/include/plat/regs-fb.h | 403 -----------------<br> include/video/samsung_fimd.h | 533 +++++++++++++++++++++++<br>
3 files changed, 533 insertions(+), 562 deletions(-)<br> delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h<br> delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb.h<br> create mode 100644 include/video/samsung_fimd.h<br>
<br>diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h<br>deleted file mode 100644<br>index 4c3647f..0000000<br>--- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h<br>
+++ /dev/null<br>@@ -1,159 +0,0 @@<br>-/* arch/arm/plat-samsung/include/plat/regs-fb-v4.h<br>- *<br>- * Copyright 2008 Openmoko, Inc.<br>- * Copyright 2008 Simtec Electronics<br>- * <a href="http://armlinux.simtec.co.uk/" target="_blank">http://armlinux.simtec.co.uk/</a><br>
- * Ben Dooks <<a href="mailto:ben@simtec.co.uk">ben@simtec.co.uk</a>><br>- *<br>- * S3C64XX - new-style framebuffer register definitions<br>- *<br>- * This is the register set for the new style framebuffer interface<br>
- * found from the S3C2443 onwards and specifically the S3C64XX series<br>- * S3C6400 and S3C6410.<br>- *<br>- * The file contains the cpu specific items which change between whichever<br>- * architecture is selected. See <plat/regs-fb.h> for the core definitions<br>
- * that are the same.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>
-*/<br>-<br>-/* include the core definitions here, in case we really do need to<br>- * override them at a later date.<br>-*/<br>-<br>-#include <plat/regs-fb.h><br>-<br>-#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */<br>
-#define VIDCON1_FSTATUS_EVEN (1 << 15)<br>-<br>-/* Video timing controls */<br>-#define VIDTCON0 (0x10)<br>-#define VIDTCON1 (0x14)<br>-#define VIDTCON2 (0x18)<br>
-<br>-/* Window position controls */<br>-<br>-#define WINCON(_win) (0x20 + ((_win) * 4))<br>-<br>-/* OSD1 and OSD4 do not have register D */<br>-<br>-#define VIDOSD_BASE (0x40)<br>
-<br>-#define VIDINTCON0 (0x130)<br>-<br>-/* WINCONx */<br>-<br>-#define WINCONx_CSCWIDTH_MASK (0x3 << 26)<br>-#define WINCONx_CSCWIDTH_SHIFT (26)<br>-#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)<br>
-#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)<br>-<br>-#define WINCONx_ENLOCAL (1 << 22)<br>-#define WINCONx_BUFSTATUS (1 << 21)<br>
-#define WINCONx_BUFSEL (1 << 20)<br>-#define WINCONx_BUFAUTOEN (1 << 19)<br>-#define WINCONx_YCbCr (1 << 13)<br>-<br>-#define WINCON1_LOCALSEL_CAMIF (1 << 23)<br>
-<br>-#define WINCON2_LOCALSEL_CAMIF (1 << 23)<br>-#define WINCON2_BLD_PIX (1 << 6)<br>-<br>-#define WINCON2_ALPHA_SEL (1 << 1)<br>-#define WINCON2_BPPMODE_MASK (0xf << 2)<br>
-#define WINCON2_BPPMODE_SHIFT (2)<br>-#define WINCON2_BPPMODE_1BPP (0x0 << 2)<br>-#define WINCON2_BPPMODE_2BPP (0x1 << 2)<br>-#define WINCON2_BPPMODE_4BPP (0x2 << 2)<br>
-#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)<br>-#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)<br>-#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)<br>-#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)<br>
-#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)<br>-#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)<br>-#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)<br>-#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)<br>
-#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)<br>-#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)<br>-#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)<br>-<br>-#define WINCON3_BLD_PIX (1 << 6)<br>
-<br>-#define WINCON3_ALPHA_SEL (1 << 1)<br>-#define WINCON3_BPPMODE_MASK (0xf << 2)<br>-#define WINCON3_BPPMODE_SHIFT (2)<br>-#define WINCON3_BPPMODE_1BPP (0x0 << 2)<br>
-#define WINCON3_BPPMODE_2BPP (0x1 << 2)<br>-#define WINCON3_BPPMODE_4BPP (0x2 << 2)<br>-#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)<br>-#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)<br>
-#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)<br>-#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)<br>-#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)<br>-#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)<br>
-#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)<br>-#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)<br>-#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)<br>-#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)<br>
-<br>-#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)<br>-#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)<br>-#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)<br>-<br>-#define DITHMODE (0x170)<br>
-#define WINxMAP(_win) (0x180 + ((_win) * 4))<br>-<br>-<br>-#define DITHMODE_R_POS_MASK (0x3 << 5)<br>-#define DITHMODE_R_POS_SHIFT (5)<br>-#define DITHMODE_R_POS_8BIT (0x0 << 5)<br>
-#define DITHMODE_R_POS_6BIT (0x1 << 5)<br>-#define DITHMODE_R_POS_5BIT (0x2 << 5)<br>-<br>-#define DITHMODE_G_POS_MASK (0x3 << 3)<br>-#define DITHMODE_G_POS_SHIFT (3)<br>
-#define DITHMODE_G_POS_8BIT (0x0 << 3)<br>-#define DITHMODE_G_POS_6BIT (0x1 << 3)<br>-#define DITHMODE_G_POS_5BIT (0x2 << 3)<br>-<br>-#define DITHMODE_B_POS_MASK (0x3 << 1)<br>
-#define DITHMODE_B_POS_SHIFT (1)<br>-#define DITHMODE_B_POS_8BIT (0x0 << 1)<br>-#define DITHMODE_B_POS_6BIT (0x1 << 1)<br>-#define DITHMODE_B_POS_5BIT (0x2 << 1)<br>
-<br>-#define DITHMODE_DITH_EN (1 << 0)<br>-<br>-#define WPALCON (0x1A0)<br>-<br>-/* Palette control */<br>-/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),<br>
- * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */<br>-#define WPALCON_W4PAL_16BPP_A555 (1 << 8)<br>-#define WPALCON_W3PAL_16BPP_A555 (1 << 7)<br>-#define WPALCON_W2PAL_16BPP_A555 (1 << 6)<br>
-<br>-<br>-/* Notes on per-window bpp settings<br>- *<br>- * Value Win0 Win1 Win2 Win3 Win 4<br>- * 0000 1(P) 1(P) 1(P) 1(P) 1(P)<br>- * 0001 2(P) 2(P) 2(P) 2(P) 2(P)<br>
- * 0010 4(P) 4(P) 4(P) 4(P) -none-<br>- * 0011 8(P) 8(P) -none- -none- -none-<br>- * 0100 -none- 8(A232) 8(A232) -none- -none-<br>- * 0101 16(565) 16(565) 16(565) 16(565) 16(565)<br>
- * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)<br>- * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)<br>- * 1000 18(666) 18(666) 18(666) 18(666) 18(666)<br>- * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)<br>
- * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)<br>- * 1011 24(888) 24(888) 24(888) 24(888) 24(888)<br>- * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)<br>- * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)<br>
- * 1110 -none- -none- -none- -none- -none-<br>- * 1111 -none- -none- -none- -none- -none-<br>-*/<br>diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h<br>
deleted file mode 100644<br>index 9a78012..0000000<br>--- a/arch/arm/plat-samsung/include/plat/regs-fb.h<br>+++ /dev/null<br>@@ -1,403 +0,0 @@<br>-/* arch/arm/plat-samsung/include/plat/regs-fb.h<br>- *<br>- * Copyright 2008 Openmoko, Inc.<br>
- * Copyright 2008 Simtec Electronics<br>- * <a href="http://armlinux.simtec.co.uk/" target="_blank">http://armlinux.simtec.co.uk/</a><br>- * Ben Dooks <<a href="mailto:ben@simtec.co.uk">ben@simtec.co.uk</a>><br>
- *<br>- * S3C Platform - new-style framebuffer register definitions<br>- *<br>- * This is the register set for the new style framebuffer interface<br>- * found from the S3C2443 onwards into the S3C2416, S3C2450 and the<br>
- * S3C64XX series such as the S3C6400 and S3C6410.<br>- *<br>- * The file does not contain the cpu specific items which are based on<br>- * whichever architecture is selected, it only contains the core of the<br>- * register set. See <mach/regs-fb.h> to get the specifics.<br>
- *<br>- * Note, we changed to using regs-fb.h as it avoids any clashes with<br>- * the original regs-lcd.h so out of the way of regs-lcd.h as well as<br>- * indicating the newer block is much more than just an LCD interface.<br>
- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License version 2 as<br>- * published by the Free Software Foundation.<br>-*/<br>-<br>-/* Please do not include this file directly, use <mach/regs-fb.h> to<br>
- * ensure all the localised SoC support is included as necessary.<br>-*/<br>-<br>-/* VIDCON0 */<br>-<br>-#define VIDCON0 (0x00)<br>-#define VIDCON0_INTERLACE (1 << 29)<br>
-#define VIDCON0_VIDOUT_MASK (0x3 << 26)<br>-#define VIDCON0_VIDOUT_SHIFT (26)<br>-#define VIDCON0_VIDOUT_RGB (0x0 << 26)<br>-#define VIDCON0_VIDOUT_TV (0x1 << 26)<br>
-#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)<br>-#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)<br>-<br>-#define VIDCON0_L1_DATA_MASK (0x7 << 23)<br>
-#define VIDCON0_L1_DATA_SHIFT (23)<br>-#define VIDCON0_L1_DATA_16BPP (0x0 << 23)<br>-#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)<br>-#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)<br>
-#define VIDCON0_L1_DATA_24BPP (0x3 << 23)<br>-#define VIDCON0_L1_DATA_18BPP (0x4 << 23)<br>-#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)<br>-<br>-#define VIDCON0_L0_DATA_MASK (0x7 << 20)<br>
-#define VIDCON0_L0_DATA_SHIFT (20)<br>-#define VIDCON0_L0_DATA_16BPP (0x0 << 20)<br>-#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)<br>-#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)<br>
-#define VIDCON0_L0_DATA_24BPP (0x3 << 20)<br>-#define VIDCON0_L0_DATA_18BPP (0x4 << 20)<br>-#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)<br>-<br>-#define VIDCON0_PNRMODE_MASK (0x3 << 17)<br>
-#define VIDCON0_PNRMODE_SHIFT (17)<br>-#define VIDCON0_PNRMODE_RGB (0x0 << 17)<br>-#define VIDCON0_PNRMODE_BGR (0x1 << 17)<br>-#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)<br>
-#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)<br>-<br>-#define VIDCON0_CLKVALUP (1 << 16)<br>-#define VIDCON0_CLKVAL_F_MASK (0xff << 6)<br>-#define VIDCON0_CLKVAL_F_SHIFT (6)<br>
-#define VIDCON0_CLKVAL_F_LIMIT (0xff)<br>-#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)<br>-#define VIDCON0_VLCKFREE (1 << 5)<br>-#define VIDCON0_CLKDIR (1 << 4)<br>
-<br>-#define VIDCON0_CLKSEL_MASK (0x3 << 2)<br>-#define VIDCON0_CLKSEL_SHIFT (2)<br>-#define VIDCON0_CLKSEL_HCLK (0x0 << 2)<br>-#define VIDCON0_CLKSEL_LCD (0x1 << 2)<br>
-#define VIDCON0_CLKSEL_27M (0x3 << 2)<br>-<br>-#define VIDCON0_ENVID (1 << 1)<br>-#define VIDCON0_ENVID_F (1 << 0)<br>-<br>-#define VIDCON1 (0x04)<br>
-#define VIDCON1_LINECNT_MASK (0x7ff << 16)<br>-#define VIDCON1_LINECNT_SHIFT (16)<br>-#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)<br>-#define VIDCON1_VSTATUS_MASK (0x3 << 13)<br>
-#define VIDCON1_VSTATUS_SHIFT (13)<br>-#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)<br>-#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)<br>-#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)<br>
-#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)<br>-#define VIDCON1_VCLK_MASK (0x3 << 9)<br>-#define VIDCON1_VCLK_HOLD (0x0 << 9)<br>-#define VIDCON1_VCLK_RUN (0x1 << 9)<br>
-<br>-#define VIDCON1_INV_VCLK (1 << 7)<br>-#define VIDCON1_INV_HSYNC (1 << 6)<br>-#define VIDCON1_INV_VSYNC (1 << 5)<br>-#define VIDCON1_INV_VDEN (1 << 4)<br>
-<br>-/* VIDCON2 */<br>-<br>-#define VIDCON2 (0x08)<br>-#define VIDCON2_EN601 (1 << 23)<br>-#define VIDCON2_TVFMTSEL_SW (1 << 14)<br>
-<br>-#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)<br>-#define VIDCON2_TVFMTSEL1_SHIFT (12)<br>-#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)<br>-#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)<br>
-#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)<br>-<br>-#define VIDCON2_ORGYCbCr (1 << 8)<br>-#define VIDCON2_YUVORDCrCb (1 << 7)<br>-<br>-/* PRTCON (S3C6410, S5PC100)<br>
- * Might not be present in the S3C6410 documentation,<br>- * but tests prove it's there almost for sure; shouldn't hurt in any case.<br>- */<br>-#define PRTCON (0x0c)<br>-#define PRTCON_PROTECT (1 << 11)<br>
-<br>-/* VIDTCON0 */<br>-<br>-#define VIDTCON0_VBPDE_MASK (0xff << 24)<br>-#define VIDTCON0_VBPDE_SHIFT (24)<br>-#define VIDTCON0_VBPDE_LIMIT (0xff)<br>-#define VIDTCON0_VBPDE(_x) ((_x) << 24)<br>
-<br>-#define VIDTCON0_VBPD_MASK (0xff << 16)<br>-#define VIDTCON0_VBPD_SHIFT (16)<br>-#define VIDTCON0_VBPD_LIMIT (0xff)<br>-#define VIDTCON0_VBPD(_x) ((_x) << 16)<br>
-<br>-#define VIDTCON0_VFPD_MASK (0xff << 8)<br>-#define VIDTCON0_VFPD_SHIFT (8)<br>-#define VIDTCON0_VFPD_LIMIT (0xff)<br>-#define VIDTCON0_VFPD(_x) ((_x) << 8)<br>
-<br>-#define VIDTCON0_VSPW_MASK (0xff << 0)<br>-#define VIDTCON0_VSPW_SHIFT (0)<br>-#define VIDTCON0_VSPW_LIMIT (0xff)<br>-#define VIDTCON0_VSPW(_x) ((_x) << 0)<br>
-<br>-/* VIDTCON1 */<br>-<br>-#define VIDTCON1_VFPDE_MASK (0xff << 24)<br>-#define VIDTCON1_VFPDE_SHIFT (24)<br>-#define VIDTCON1_VFPDE_LIMIT (0xff)<br>-#define VIDTCON1_VFPDE(_x) ((_x) << 24)<br>
-<br>-#define VIDTCON1_HBPD_MASK (0xff << 16)<br>-#define VIDTCON1_HBPD_SHIFT (16)<br>-#define VIDTCON1_HBPD_LIMIT (0xff)<br>-#define VIDTCON1_HBPD(_x) ((_x) << 16)<br>
-<br>-#define VIDTCON1_HFPD_MASK (0xff << 8)<br>-#define VIDTCON1_HFPD_SHIFT (8)<br>-#define VIDTCON1_HFPD_LIMIT (0xff)<br>-#define VIDTCON1_HFPD(_x) ((_x) << 8)<br>
-<br>-#define VIDTCON1_HSPW_MASK (0xff << 0)<br>-#define VIDTCON1_HSPW_SHIFT (0)<br>-#define VIDTCON1_HSPW_LIMIT (0xff)<br>-#define VIDTCON1_HSPW(_x) ((_x) << 0)<br>
-<br>-#define VIDTCON2 (0x18)<br>-#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)<br>-#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)<br>
-#define VIDTCON2_LINEVAL_SHIFT (11)<br>-#define VIDTCON2_LINEVAL_LIMIT (0x7ff)<br>-#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)<br>-<br>-#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)<br>
-#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)<br>-#define VIDTCON2_HOZVAL_SHIFT (0)<br>-#define VIDTCON2_HOZVAL_LIMIT (0x7ff)<br>-#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)<br>
-<br>-/* WINCONx */<br>-<br>-<br>-#define WINCONx_BITSWP (1 << 18)<br>-#define WINCONx_BYTSWP (1 << 17)<br>-#define WINCONx_HAWSWP (1 << 16)<br>
-#define WINCONx_WSWP (1 << 15)<br>-#define WINCONx_BURSTLEN_MASK (0x3 << 9)<br>-#define WINCONx_BURSTLEN_SHIFT (9)<br>-#define WINCONx_BURSTLEN_16WORD (0x0 << 9)<br>
-#define WINCONx_BURSTLEN_8WORD (0x1 << 9)<br>-#define WINCONx_BURSTLEN_4WORD (0x2 << 9)<br>-<br>-#define WINCONx_ENWIN (1 << 0)<br>-#define WINCON0_BPPMODE_MASK (0xf << 2)<br>
-#define WINCON0_BPPMODE_SHIFT (2)<br>-#define WINCON0_BPPMODE_1BPP (0x0 << 2)<br>-#define WINCON0_BPPMODE_2BPP (0x1 << 2)<br>-#define WINCON0_BPPMODE_4BPP (0x2 << 2)<br>
-#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)<br>-#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)<br>-#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)<br>-#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)<br>
-#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)<br>-<br>-#define WINCON1_BLD_PIX (1 << 6)<br>-<br>-#define WINCON1_ALPHA_SEL (1 << 1)<br>-#define WINCON1_BPPMODE_MASK (0xf << 2)<br>
-#define WINCON1_BPPMODE_SHIFT (2)<br>-#define WINCON1_BPPMODE_1BPP (0x0 << 2)<br>-#define WINCON1_BPPMODE_2BPP (0x1 << 2)<br>-#define WINCON1_BPPMODE_4BPP (0x2 << 2)<br>
-#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)<br>-#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)<br>-#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)<br>-#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)<br>
-#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)<br>-#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)<br>-#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)<br>-#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)<br>
-#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)<br>-#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)<br>-#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)<br>-#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)<br>
-<br>-/* S5PV210 */<br>-#define SHADOWCON (0x34)<br>-#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))<br>-/* DMA channels (all windows) */<br>-#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))<br>
-/* Local input channels (windows 0-2) */<br>-#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))<br>-<br>-#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)<br>
-#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)<br>-#define VIDOSDxA_TOPLEFT_X_SHIFT (11)<br>-#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)<br>-#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)<br>
-<br>-#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)<br>-#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)<br>-#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)<br>
-#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)<br>-#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)<br>-<br>-#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)<br>
-#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)<br>-#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)<br>-#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)<br>-#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)<br>
-<br>-#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)<br>-#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)<br>-#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)<br>
-#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)<br>-#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)<br>-<br>-/* For VIDOSD[1..4]C */<br>-#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)<br>
-#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)<br>-#define VIDISD14C_ALPHA0_G_SHIFT (16)<br>-#define VIDISD14C_ALPHA0_G_LIMIT (0xf)<br>-#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)<br>
-#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)<br>-#define VIDISD14C_ALPHA0_B_SHIFT (12)<br>-#define VIDISD14C_ALPHA0_B_LIMIT (0xf)<br>-#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)<br>
-#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)<br>-#define VIDISD14C_ALPHA1_R_SHIFT (8)<br>-#define VIDISD14C_ALPHA1_R_LIMIT (0xf)<br>-#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)<br>
-#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)<br>-#define VIDISD14C_ALPHA1_G_SHIFT (4)<br>-#define VIDISD14C_ALPHA1_G_LIMIT (0xf)<br>-#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)<br>
-#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)<br>-#define VIDISD14C_ALPHA1_B_SHIFT (0)<br>-#define VIDISD14C_ALPHA1_B_LIMIT (0xf)<br>-#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)<br>
-<br>-/* Video buffer addresses */<br>-#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))<br>-#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))<br>-#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))<br>
-#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))<br>-#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))<br>-<br>-#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)<br>
-#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)<br>-#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)<br>-#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)<br>-#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)<br>
-<br>-#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)<br>-#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)<br>-#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)<br>
-#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)<br>-#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)<br>-<br>-/* Interrupt controls and status */<br>-<br>-#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)<br>
-#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)<br>-#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)<br>-#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)<br>-<br>-#define VIDINTCON0_INT_SYSMAINCON (1 << 19)<br>
-#define VIDINTCON0_INT_SYSSUBCON (1 << 18)<br>-#define VIDINTCON0_INT_I80IFDONE (1 << 17)<br>-<br>-#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)<br>-#define VIDINTCON0_FRAMESEL0_SHIFT (15)<br>
-#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)<br>-#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)<br>-#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)<br>-#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)<br>
-<br>-#define VIDINTCON0_FRAMESEL1 (1 << 13)<br>-#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)<br>-#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)<br>-#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)<br>
-#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)<br>-#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)<br>-<br>-#define VIDINTCON0_INT_FRAME (1 << 12)<br>-#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)<br>
-#define VIDINTCON0_FIFIOSEL_SHIFT (5)<br>-#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)<br>-#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)<br>-<br>-#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)<br>
-#define VIDINTCON0_FIFOLEVEL_SHIFT (2)<br>-#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)<br>-#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)<br>-#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)<br>
-#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)<br>-#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)<br>-<br>-#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)<br>-#define VIDINTCON0_INT_FIFO_SHIFT (0)<br>
-#define VIDINTCON0_INT_ENABLE (1 << 0)<br>-<br>-#define VIDINTCON1 (0x134)<br>-#define VIDINTCON1_INT_I180 (1 << 2)<br>-#define VIDINTCON1_INT_FRAME (1 << 1)<br>
-#define VIDINTCON1_INT_FIFO (1 << 0)<br>-<br>-/* Window colour-key control registers */<br>-#define WKEYCON (0x140) /* 6410,V210 */<br>-<br>-#define WKEYCON0 (0x00)<br>
-#define WKEYCON1 (0x04)<br>-<br>-#define WxKEYCON0_KEYBL_EN (1 << 26)<br>-#define WxKEYCON0_KEYEN_F (1 << 25)<br>-#define WxKEYCON0_DIRCON (1 << 24)<br>
-#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)<br>-#define WxKEYCON0_COMPKEY_SHIFT (0)<br>-#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)<br>-#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)<br>
-#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)<br>-#define WxKEYCON1_COLVAL_SHIFT (0)<br>-#define WxKEYCON1_COLVAL_LIMIT (0xffffff)<br>-#define WxKEYCON1_COLVAL(_x) ((_x) << 0)<br>
-<br>-<br>-/* Window blanking (MAP) */<br>-<br>-#define WINxMAP_MAP (1 << 24)<br>-#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)<br>-#define WINxMAP_MAP_COLOUR_SHIFT (0)<br>
-#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)<br>-#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)<br>-<br>-#define WPALCON_PAL_UPDATE (1 << 9)<br>-#define WPALCON_W1PAL_MASK (0x7 << 3)<br>
-#define WPALCON_W1PAL_SHIFT (3)<br>-#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)<br>-#define WPALCON_W1PAL_24BPP (0x1 << 3)<br>-#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)<br>
-#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)<br>-#define WPALCON_W1PAL_18BPP (0x4 << 3)<br>-#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)<br>-#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)<br>
-<br>-#define WPALCON_W0PAL_MASK (0x7 << 0)<br>-#define WPALCON_W0PAL_SHIFT (0)<br>-#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)<br>-#define WPALCON_W0PAL_24BPP (0x1 << 0)<br>
-#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)<br>-#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)<br>-#define WPALCON_W0PAL_18BPP (0x4 << 0)<br>-#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)<br>
-#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)<br>-<br>-/* Blending equation control */<br>-#define BLENDCON (0x260)<br>-#define BLENDCON_NEW_MASK (1 << 0)<br>
-#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)<br>-#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)<br>-<br>diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h<br>new file mode 100644<br>
index 0000000..1b5ff4c<br>--- /dev/null<br>+++ b/include/video/samsung_fimd.h<br>@@ -0,0 +1,533 @@<br>+/* include/video/samsung_fimd.h<br>+ *<br>+ * Copyright 2008 Openmoko, Inc.<br>+ * Copyright 2008 Simtec Electronics<br>
+ * <a href="http://armlinux.simtec.co.uk/" target="_blank">http://armlinux.simtec.co.uk/</a><br>+ * Ben Dooks <<a href="mailto:ben@simtec.co.uk">ben@simtec.co.uk</a>><br>+ *<br>+ * S3C Platform - new-style fimd and framebuffer register definitions<br>
+ *<br>+ * This is the register set for the fimd and new style framebuffer interface<br>+ * found from the S3C2443 onwards into the S3C2416, S3C2450 and the<br>+ * S3C64XX series such as the S3C6400 and S3C6410.<br>+ *<br>
+ * The file does not contain the cpu specific items which are based on<br>+ * whichever architecture is selected, it only contains the core of the<br>+ * register set. See <mach/regs-fb.h> to get the specifics.<br>
+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License version 2 as<br>+ * published by the Free Software Foundation.<br>+*/<br>+<br>+/* VIDCON0 */<br>
+<br>+#define VIDCON0 (0x00)<br>+#define VIDCON0_INTERLACE (1 << 29)<br>+#define VIDCON0_VIDOUT_MASK (0x3 << 26)<br>+#define VIDCON0_VIDOUT_SHIFT (26)<br>
+#define VIDCON0_VIDOUT_RGB (0x0 << 26)<br>+#define VIDCON0_VIDOUT_TV (0x1 << 26)<br>+#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)<br>+#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)<br>
+<br>+#define VIDCON0_L1_DATA_MASK (0x7 << 23)<br>+#define VIDCON0_L1_DATA_SHIFT (23)<br>+#define VIDCON0_L1_DATA_16BPP (0x0 << 23)<br>+#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)<br>
+#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)<br>+#define VIDCON0_L1_DATA_24BPP (0x3 << 23)<br>+#define VIDCON0_L1_DATA_18BPP (0x4 << 23)<br>+#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)<br>
+<br>+#define VIDCON0_L0_DATA_MASK (0x7 << 20)<br>+#define VIDCON0_L0_DATA_SHIFT (20)<br>+#define VIDCON0_L0_DATA_16BPP (0x0 << 20)<br>+#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)<br>
+#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)<br>+#define VIDCON0_L0_DATA_24BPP (0x3 << 20)<br>+#define VIDCON0_L0_DATA_18BPP (0x4 << 20)<br>+#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)<br>
+<br>+#define VIDCON0_PNRMODE_MASK (0x3 << 17)<br>+#define VIDCON0_PNRMODE_SHIFT (17)<br>+#define VIDCON0_PNRMODE_RGB (0x0 << 17)<br>+#define VIDCON0_PNRMODE_BGR (0x1 << 17)<br>
+#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)<br>+#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)<br>+<br>+#define VIDCON0_CLKVALUP (1 << 16)<br>+#define VIDCON0_CLKVAL_F_MASK (0xff << 6)<br>
+#define VIDCON0_CLKVAL_F_SHIFT (6)<br>+#define VIDCON0_CLKVAL_F_LIMIT (0xff)<br>+#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)<br>+#define VIDCON0_VLCKFREE (1 << 5)<br>
+#define VIDCON0_CLKDIR (1 << 4)<br>+<br>+#define VIDCON0_CLKSEL_MASK (0x3 << 2)<br>+#define VIDCON0_CLKSEL_SHIFT (2)<br>+#define VIDCON0_CLKSEL_HCLK (0x0 << 2)<br>
+#define VIDCON0_CLKSEL_LCD (0x1 << 2)<br>+#define VIDCON0_CLKSEL_27M (0x3 << 2)<br>+<br>+#define VIDCON0_ENVID (1 << 1)<br>+#define VIDCON0_ENVID_F (1 << 0)<br>
+<br>+#define VIDCON1 (0x04)<br>+#define VIDCON1_LINECNT_MASK (0x7ff << 16)<br>+#define VIDCON1_LINECNT_SHIFT (16)<br>+#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)<br>
+#define VIDCON1_VSTATUS_MASK (0x3 << 13)<br>+#define VIDCON1_VSTATUS_SHIFT (13)<br>+#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)<br>+#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)<br>
+#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)<br>+#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)<br>+#define VIDCON1_VCLK_MASK (0x3 << 9)<br>+#define VIDCON1_VCLK_HOLD (0x0 << 9)<br>
+#define VIDCON1_VCLK_RUN (0x1 << 9)<br>+<br>+#define VIDCON1_INV_VCLK (1 << 7)<br>+#define VIDCON1_INV_HSYNC (1 << 6)<br>+#define VIDCON1_INV_VSYNC (1 << 5)<br>
+#define VIDCON1_INV_VDEN (1 << 4)<br>+<br>+/* VIDCON2 */<br>+<br>+#define VIDCON2 (0x08)<br>+#define VIDCON2_EN601 (1 << 23)<br>
+#define VIDCON2_TVFMTSEL_SW (1 << 14)<br>+<br>+#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)<br>+#define VIDCON2_TVFMTSEL1_SHIFT (12)<br>+#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)<br>
+#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)<br>+#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)<br>+<br>+#define VIDCON2_ORGYCbCr (1 << 8)<br>+#define VIDCON2_YUVORDCrCb (1 << 7)<br>
+<br>+/* PRTCON (S3C6410, S5PC100)<br>+ * Might not be present in the S3C6410 documentation,<br>+ * but tests prove it's there almost for sure; shouldn't hurt in any case.<br>+ */<br>+#define PRTCON (0x0c)<br>
+#define PRTCON_PROTECT (1 << 11)<br>+<br>+/* VIDTCON0 */<br>+<br>+#define VIDTCON0_VBPDE_MASK (0xff << 24)<br>+#define VIDTCON0_VBPDE_SHIFT (24)<br>
+#define VIDTCON0_VBPDE_LIMIT (0xff)<br>+#define VIDTCON0_VBPDE(_x) ((_x) << 24)<br>+<br>+#define VIDTCON0_VBPD_MASK (0xff << 16)<br>+#define VIDTCON0_VBPD_SHIFT (16)<br>
+#define VIDTCON0_VBPD_LIMIT (0xff)<br>+#define VIDTCON0_VBPD(_x) ((_x) << 16)<br>+<br>+#define VIDTCON0_VFPD_MASK (0xff << 8)<br>+#define VIDTCON0_VFPD_SHIFT (8)<br>
+#define VIDTCON0_VFPD_LIMIT (0xff)<br>+#define VIDTCON0_VFPD(_x) ((_x) << 8)<br>+<br>+#define VIDTCON0_VSPW_MASK (0xff << 0)<br>+#define VIDTCON0_VSPW_SHIFT (0)<br>
+#define VIDTCON0_VSPW_LIMIT (0xff)<br>+#define VIDTCON0_VSPW(_x) ((_x) << 0)<br>+<br>+/* VIDTCON1 */<br>+<br>+#define VIDTCON1_VFPDE_MASK (0xff << 24)<br>
+#define VIDTCON1_VFPDE_SHIFT (24)<br>+#define VIDTCON1_VFPDE_LIMIT (0xff)<br>+#define VIDTCON1_VFPDE(_x) ((_x) << 24)<br>+<br>+#define VIDTCON1_HBPD_MASK (0xff << 16)<br>
+#define VIDTCON1_HBPD_SHIFT (16)<br>+#define VIDTCON1_HBPD_LIMIT (0xff)<br>+#define VIDTCON1_HBPD(_x) ((_x) << 16)<br>+<br>+#define VIDTCON1_HFPD_MASK (0xff << 8)<br>
+#define VIDTCON1_HFPD_SHIFT (8)<br>+#define VIDTCON1_HFPD_LIMIT (0xff)<br>+#define VIDTCON1_HFPD(_x) ((_x) << 8)<br>+<br>+#define VIDTCON1_HSPW_MASK (0xff << 0)<br>
+#define VIDTCON1_HSPW_SHIFT (0)<br>+#define VIDTCON1_HSPW_LIMIT (0xff)<br>+#define VIDTCON1_HSPW(_x) ((_x) << 0)<br>+<br>+#define VIDTCON2 (0x18)<br>
+#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)<br>+#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)<br>+#define VIDTCON2_LINEVAL_SHIFT (11)<br>
+#define VIDTCON2_LINEVAL_LIMIT (0x7ff)<br>+#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)<br>+<br>+#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)<br>
+#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)<br>+#define VIDTCON2_HOZVAL_SHIFT (0)<br>+#define VIDTCON2_HOZVAL_LIMIT (0x7ff)<br>+#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)<br>
+<br>+/* WINCONx */<br>+<br>+<br>+#define WINCONx_BITSWP (1 << 18)<br>+#define WINCONx_BYTSWP (1 << 17)<br>+#define WINCONx_HAWSWP (1 << 16)<br>
+#define WINCONx_WSWP (1 << 15)<br>+#define WINCONx_BURSTLEN_MASK (0x3 << 9)<br>+#define WINCONx_BURSTLEN_SHIFT (9)<br>+#define WINCONx_BURSTLEN_16WORD (0x0 << 9)<br>
+#define WINCONx_BURSTLEN_8WORD (0x1 << 9)<br>+#define WINCONx_BURSTLEN_4WORD (0x2 << 9)<br>+<br>+#define WINCONx_ENWIN (1 << 0)<br>+#define WINCON0_BPPMODE_MASK (0xf << 2)<br>
+#define WINCON0_BPPMODE_SHIFT (2)<br>+#define WINCON0_BPPMODE_1BPP (0x0 << 2)<br>+#define WINCON0_BPPMODE_2BPP (0x1 << 2)<br>+#define WINCON0_BPPMODE_4BPP (0x2 << 2)<br>
+#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)<br>+#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)<br>+#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)<br>+#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)<br>
+#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)<br>+<br>+#define WINCON1_BLD_PIX (1 << 6)<br>+<br>+#define WINCON1_ALPHA_SEL (1 << 1)<br>+#define WINCON1_BPPMODE_MASK (0xf << 2)<br>
+#define WINCON1_BPPMODE_SHIFT (2)<br>+#define WINCON1_BPPMODE_1BPP (0x0 << 2)<br>+#define WINCON1_BPPMODE_2BPP (0x1 << 2)<br>+#define WINCON1_BPPMODE_4BPP (0x2 << 2)<br>
+#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)<br>+#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)<br>+#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)<br>+#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)<br>
+#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)<br>+#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)<br>+#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)<br>+#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)<br>
+#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)<br>+#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)<br>+#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)<br>+#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)<br>
+<br>+/* S5PV210 */<br>+#define SHADOWCON (0x34)<br>+#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))<br>+/* DMA channels (all windows) */<br>+#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))<br>
+/* Local input channels (windows 0-2) */<br>+#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))<br>+<br>+#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)<br>
+#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)<br>+#define VIDOSDxA_TOPLEFT_X_SHIFT (11)<br>+#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)<br>+#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)<br>
+<br>+#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)<br>+#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)<br>+#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)<br>
+#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)<br>+#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)<br>+<br>+#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)<br>
+#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)<br>+#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)<br>+#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)<br>+#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)<br>
+<br>+#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)<br>+#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)<br>+#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)<br>
+#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)<br>+#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)<br>+<br>+/* For VIDOSD[1..4]C */<br>+#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)<br>
+#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)<br>+#define VIDISD14C_ALPHA0_G_SHIFT (16)<br>+#define VIDISD14C_ALPHA0_G_LIMIT (0xf)<br>+#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)<br>
+#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)<br>+#define VIDISD14C_ALPHA0_B_SHIFT (12)<br>+#define VIDISD14C_ALPHA0_B_LIMIT (0xf)<br>+#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)<br>
+#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)<br>+#define VIDISD14C_ALPHA1_R_SHIFT (8)<br>+#define VIDISD14C_ALPHA1_R_LIMIT (0xf)<br>+#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)<br>
+#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)<br>+#define VIDISD14C_ALPHA1_G_SHIFT (4)<br>+#define VIDISD14C_ALPHA1_G_LIMIT (0xf)<br>+#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)<br>
+#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)<br>+#define VIDISD14C_ALPHA1_B_SHIFT (0)<br>+#define VIDISD14C_ALPHA1_B_LIMIT (0xf)<br>+#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)<br>
+<br>+/* Video buffer addresses */<br>+#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))<br>+#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))<br>+#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))<br>
+#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))<br>+#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))<br>+<br>+#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)<br>
+#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)<br>+#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)<br>+#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)<br>+#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)<br>
+<br>+#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)<br>+#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)<br>+#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)<br>
+#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)<br>+#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)<br>+<br>+/* Interrupt controls and status */<br>+<br>+#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)<br>
+#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)<br>+#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)<br>+#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)<br>+<br>+#define VIDINTCON0_INT_SYSMAINCON (1 << 19)<br>
+#define VIDINTCON0_INT_SYSSUBCON (1 << 18)<br>+#define VIDINTCON0_INT_I80IFDONE (1 << 17)<br>+<br>+#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)<br>+#define VIDINTCON0_FRAMESEL0_SHIFT (15)<br>
+#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)<br>+#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)<br>+#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)<br>+#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)<br>
+<br>+#define VIDINTCON0_FRAMESEL1 (1 << 13)<br>+#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)<br>+#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)<br>+#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)<br>
+#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)<br>+#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)<br>+<br>+#define VIDINTCON0_INT_FRAME (1 << 12)<br>+#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)<br>
+#define VIDINTCON0_FIFIOSEL_SHIFT (5)<br>+#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)<br>+#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)<br>+<br>+#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)<br>
+#define VIDINTCON0_FIFOLEVEL_SHIFT (2)<br>+#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)<br>+#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)<br>+#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)<br>
+#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)<br>+#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)<br>+<br>+#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)<br>+#define VIDINTCON0_INT_FIFO_SHIFT (0)<br>
+#define VIDINTCON0_INT_ENABLE (1 << 0)<br>+<br>+#define VIDINTCON1 (0x134)<br>+#define VIDINTCON1_INT_I180 (1 << 2)<br>+#define VIDINTCON1_INT_FRAME (1 << 1)<br>
+#define VIDINTCON1_INT_FIFO (1 << 0)<br>+<br>+/* Window colour-key control registers */<br>+#define WKEYCON (0x140) /* 6410,V210 */<br>+<br>+#define WKEYCON0 (0x00)<br>
+#define WKEYCON1 (0x04)<br>+<br>+#define WxKEYCON0_KEYBL_EN (1 << 26)<br>+#define WxKEYCON0_KEYEN_F (1 << 25)<br>+#define WxKEYCON0_DIRCON (1 << 24)<br>
+#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)<br>+#define WxKEYCON0_COMPKEY_SHIFT (0)<br>+#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)<br>+#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)<br>
+#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)<br>+#define WxKEYCON1_COLVAL_SHIFT (0)<br>+#define WxKEYCON1_COLVAL_LIMIT (0xffffff)<br>+#define WxKEYCON1_COLVAL(_x) ((_x) << 0)<br>
+<br>+<br>+/* Window blanking (MAP) */<br>+<br>+#define WINxMAP_MAP (1 << 24)<br>+#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)<br>+#define WINxMAP_MAP_COLOUR_SHIFT (0)<br>
+#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)<br>+#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)<br>+<br>+#define WPALCON_PAL_UPDATE (1 << 9)<br>+#define WPALCON_W1PAL_MASK (0x7 << 3)<br>
+#define WPALCON_W1PAL_SHIFT (3)<br>+#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)<br>+#define WPALCON_W1PAL_24BPP (0x1 << 3)<br>+#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)<br>
+#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)<br>+#define WPALCON_W1PAL_18BPP (0x4 << 3)<br>+#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)<br>+#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)<br>
+<br>+#define WPALCON_W0PAL_MASK (0x7 << 0)<br>+#define WPALCON_W0PAL_SHIFT (0)<br>+#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)<br>+#define WPALCON_W0PAL_24BPP (0x1 << 0)<br>
+#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)<br>+#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)<br>+#define WPALCON_W0PAL_18BPP (0x4 << 0)<br>+#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)<br>
+#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)<br>+<br>+/* Blending equation control */<br>+#define BLENDCON (0x260)<br>+#define BLENDCON_NEW_MASK (1 << 0)<br>
+#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)<br>+#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)<br>+<br>+#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */<br>+#define VIDCON1_FSTATUS_EVEN (1 << 15)<br>
+<br>+/* Video timing controls */<br>+#define VIDTCON0 (0x10)<br>+#define VIDTCON1 (0x14)<br>+#define VIDTCON2 (0x18)<br>+<br>+/* Window position controls */<br>
+<br>+#define WINCON(_win) (0x20 + ((_win) * 4))<br>+<br>+/* OSD1 and OSD4 do not have register D */<br>+<br>+#define VIDOSD_BASE (0x40)<br>+<br>+#define VIDINTCON0 (0x130)<br>
+<br>+/* WINCONx */<br>+<br>+#define WINCONx_CSCWIDTH_MASK (0x3 << 26)<br>+#define WINCONx_CSCWIDTH_SHIFT (26)<br>+#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)<br>
+#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)<br>+<br>+#define WINCONx_ENLOCAL (1 << 22)<br>+#define WINCONx_BUFSTATUS (1 << 21)<br>
+#define WINCONx_BUFSEL (1 << 20)<br>+#define WINCONx_BUFAUTOEN (1 << 19)<br>+#define WINCONx_YCbCr (1 << 13)<br>+<br>+#define WINCON1_LOCALSEL_CAMIF (1 << 23)<br>
+<br>+#define WINCON2_LOCALSEL_CAMIF (1 << 23)<br>+#define WINCON2_BLD_PIX (1 << 6)<br>+<br>+#define WINCON2_ALPHA_SEL (1 << 1)<br>+#define WINCON2_BPPMODE_MASK (0xf << 2)<br>
+#define WINCON2_BPPMODE_SHIFT (2)<br>+#define WINCON2_BPPMODE_1BPP (0x0 << 2)<br>+#define WINCON2_BPPMODE_2BPP (0x1 << 2)<br>+#define WINCON2_BPPMODE_4BPP (0x2 << 2)<br>
+#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)<br>+#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)<br>+#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)<br>+#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)<br>
+#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)<br>+#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)<br>+#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)<br>+#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)<br>
+#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)<br>+#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)<br>+#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)<br>+<br>+#define WINCON3_BLD_PIX (1 << 6)<br>
+<br>+#define WINCON3_ALPHA_SEL (1 << 1)<br>+#define WINCON3_BPPMODE_MASK (0xf << 2)<br>+#define WINCON3_BPPMODE_SHIFT (2)<br>+#define WINCON3_BPPMODE_1BPP (0x0 << 2)<br>
+#define WINCON3_BPPMODE_2BPP (0x1 << 2)<br>+#define WINCON3_BPPMODE_4BPP (0x2 << 2)<br>+#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)<br>+#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)<br>
+#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)<br>+#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)<br>+#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)<br>+#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)<br>
+#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)<br>+#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)<br>+#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)<br>+#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)<br>
+<br>+#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)<br>+#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)<br>+#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)<br>+<br>+#define DITHMODE (0x170)<br>
+#define WINxMAP(_win) (0x180 + ((_win) * 4))<br>+<br>+<br>+#define DITHMODE_R_POS_MASK (0x3 << 5)<br>+#define DITHMODE_R_POS_SHIFT (5)<br>+#define DITHMODE_R_POS_8BIT (0x0 << 5)<br>
+#define DITHMODE_R_POS_6BIT (0x1 << 5)<br>+#define DITHMODE_R_POS_5BIT (0x2 << 5)<br>+<br>+#define DITHMODE_G_POS_MASK (0x3 << 3)<br>+#define DITHMODE_G_POS_SHIFT (3)<br>
+#define DITHMODE_G_POS_8BIT (0x0 << 3)<br>+#define DITHMODE_G_POS_6BIT (0x1 << 3)<br>+#define DITHMODE_G_POS_5BIT (0x2 << 3)<br>+<br>+#define DITHMODE_B_POS_MASK (0x3 << 1)<br>
+#define DITHMODE_B_POS_SHIFT (1)<br>+#define DITHMODE_B_POS_8BIT (0x0 << 1)<br>+#define DITHMODE_B_POS_6BIT (0x1 << 1)<br>+#define DITHMODE_B_POS_5BIT (0x2 << 1)<br>
+<br>+#define DITHMODE_DITH_EN (1 << 0)<br>+<br>+#define WPALCON (0x1A0)<br>+<br>+/* Palette control */<br>+/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),<br>
+ * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */<br>+#define WPALCON_W4PAL_16BPP_A555 (1 << 8)<br>+#define WPALCON_W3PAL_16BPP_A555 (1 << 7)<br>+#define WPALCON_W2PAL_16BPP_A555 (1 << 6)<br>
+<br>+<br>+/* Notes on per-window bpp settings<br>+ *<br>+ * Value Win0 Win1 Win2 Win3 Win 4<br>+ * 0000 1(P) 1(P) 1(P) 1(P) 1(P)<br>+ * 0001 2(P) 2(P) 2(P) 2(P) 2(P)<br>
+ * 0010 4(P) 4(P) 4(P) 4(P) -none-<br>+ * 0011 8(P) 8(P) -none- -none- -none-<br>+ * 0100 -none- 8(A232) 8(A232) -none- -none-<br>+ * 0101 16(565) 16(565) 16(565) 16(565) 16(565)<br>
+ * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)<br>+ * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)<br>+ * 1000 18(666) 18(666) 18(666) 18(666) 18(666)<br>+ * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)<br>
+ * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)<br>+ * 1011 24(888) 24(888) 24(888) 24(888) 24(888)<br>+ * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)<br>+ * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)<br>
+ * 1110 -none- -none- -none- -none- -none-<br>+ * 1111 -none- -none- -none- -none- -none-<br>+*/<br>+<br>+/*FIMD V8 REG OFFSET */<br>+#define FIMD_V8_VIDTCON0 (0x20010)<br>
+#define FIMD_V8_VIDTCON1 (0x20014)<br>+#define FIMD_V8_VIDTCON2 (0x20018)<br>+#define FIMD_V8_VIDTCON3 (0x2001C)<br>+#define FIMD_V8_VIDCON1 (0x20004)<br><span class="HOEnZb"><font color="#888888">--<br>
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</font></span></blockquote></div><br>