<HTML><BODY>Hello.<br><br><br>Wed, 11 Jul 2012 08:44:06 +0200 от Sascha Hauer <s.hauer@pengutronix.de>:<br>
<blockquote style="border-left: 1px solid rgb(8, 87, 166); margin: 10px; padding: 0pt 0pt 0pt 10px;" class="mailru-blockquote"><div id=""><div class="js-helper js-readmsg-msg"><div id="style_13419890500000000312" class="mr_read__body"><div id="style_13419890500000000312_BODY">On Tue, Jul 10, 2012 at 10:54:29PM +0400, Alexander Shiyan wrote:<br>
> This patch fix incorrect defined bits for GPT clocks according to<br>
> datasheet.<br><br>
Fix is a strong word. As I can see it these are only cosmetic changes<br>
without any functional change, right?</div></div></div></div></blockquote>No. GPT bits for "per_root" and "ipg" was be swapped. IMX51RM says:<br>CCGR2 Register Mapping<br>...<br>9 gpt_ipg_clk<br>10 gpt_highfreq<br>...<br><br style="overflow: auto;" dir="ltr" id="tinymce" class="mceContentBody " contenteditable="true"><blockquote style="border-left: 1px solid rgb(8, 87, 166); margin: 10px; padding: 0pt 0pt 0pt 10px;" class="mailru-blockquote"><div id=""><div class="js-helper js-readmsg-msg"><div id="style_13419890500000000312" class="mr_read__body"><div id="style_13419890500000000312_BODY"><br>
> Signed-off-by: Alexander Shiyan <<a href="sentmsg?compose&To=shc_work@mail.ru">shc_work@mail.ru</a>><br>
> ---<br>
> arch/arm/mach-imx/clk-imx51-imx53.c | 8 ++++----<br>
> 1 files changed, 4 insertions(+), 4 deletions(-)<br>
> <br>
> diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c<br>
> index 50e6043..628e940 100644<br>
> --- a/arch/arm/mach-imx/clk-imx51-imx53.c<br>
> +++ b/arch/arm/mach-imx/clk-imx51-imx53.c<br>
> @@ -58,7 +58,7 @@ enum imx5_clks {<br>
> tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,<br>
> uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,<br>
> gpt_ipg_gate, pwm1_ipg_gate, pwm1_per_gate, pwm2_ipg_gate, pwm2_per_gate,<br>
> - gpt_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,<br>
> + gpt_per_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,<br>
> esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,<br>
> ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,<br>
> ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,<br>
> @@ -168,12 +168,12 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,<br>
> clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);<br>
> clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);<br>
> clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);<br>
> - clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 20);<br>
> clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);<br>
> clk[pwm1_per_gate] = imx_clk_gate2("pwm1_per_gate", "per_root", MXC_CCM_CCGR2, 12);<br>
> clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);<br>
> clk[pwm2_per_gate] = imx_clk_gate2("pwm2_per_gate", "per_root", MXC_CCM_CCGR2, 16);<br>
> - clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per_root", MXC_CCM_CCGR2, 18);<br>
> + clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);<br>
> + clk[gpt_per_gate] = imx_clk_gate2("gpt_per_gate", "per_root", MXC_CCM_CCGR2, 20);<br>
> clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);<br>
> clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);<br>
> clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);<br>
> @@ -237,7 +237,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,<br>
> pr_err("i.MX5 clk %d: register failed with %ld\n",<br>
> i, PTR_ERR(clk[i]));<br>
> <br>
> - clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");<br>
> + clk_register_clkdev(clk[gpt_per_gate], "per", "imx-gpt.0");<br>
> clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");<br>
> clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");<br>
> clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");<br>
> -- <br>
> 1.7.3.4<br>
> <br>
> <br><br>
-- <br>
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