<html>
<head>
<meta content="text/html; charset=ISO-8859-1"
http-equiv="Content-Type">
</head>
<body bgcolor="#FFFFFF" text="#000000">
Hi,<br>
<br>
On 06/27/2012 08:57 AM, Boojin Kim wrote:
<blockquote
cite="mid:006d01cd53f7$6877ed90$3967c8b0$%25kim@samsung.com"
type="cite">
<pre wrap="">Joonyoung Shim wrote:
</pre>
<blockquote type="cite">
<pre wrap="">I don't understand this. Do you mean that BL1 codes do it?
I also wonder how enable L2 cache at the exynos5.
</pre>
</blockquote>
<pre wrap="">Yes, the latency configuration of L2 cache is located on IROM or BL1 code.</pre>
</blockquote>
<br>
How does kernel know it? Also, IROM and BL1 is blackbox to me<br>
<br>
<blockquote
cite="mid:006d01cd53f7$6877ed90$3967c8b0$%25kim@samsung.com"
type="cite">
<pre wrap="">
It can remove the overhead about cache reset and cache flush.
And, Kernel enables L2 cache.</pre>
</blockquote>
<br>
I cannot find codes to enable L2 cache for exynos5 in the kernel.<br>
Please let me know it.<br>
<br>
Thanks.<br>
<br>
<blockquote
cite="mid:006d01cd53f7$6877ed90$3967c8b0$%25kim@samsung.com"
type="cite">
<pre wrap="">
Thanks.
</pre>
<blockquote type="cite">
<pre wrap="">
</pre>
<blockquote type="cite">
<pre wrap="">no longer need that in the kernel. It helps to reduce
booting time (no need cache disable and cache enable).
Signed-off-by: Boojin Kim <a class="moz-txt-link-rfc2396E" href="mailto:boojin.kim@samsung.com"><boojin.kim@samsung.com></a>
Signed-off-by: Kukjin Kim <a class="moz-txt-link-rfc2396E" href="mailto:kgene.kim@samsung.com"><kgene.kim@samsung.com></a>
---
쟞rch/arm/mach-exynos/common.c | 25 -------------------------
1 files changed, 0 insertions(+), 25 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 742edd3..0ec1a91 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -712,31 +712,6 @@ static int __init exynos4_l2x0_cache_init(void)
쟢arly_initcall(exynos4_l2x0_cache_init);
#endif
-static int __init exynos5_l2_cache_init(void)
-{
- unsigned int val;
-
- if (!soc_is_exynos5250())
- return 0;
-
- asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
- "bic %0, %0, #(1 << 2)\n" /* cache disable */
- "mcr p15, 0, %0, c1, c0, 0\n"
- "mrc p15, 1, %0, c9, c0, 2\n"
- : "=r"(val));
-
- val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
-
- asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
- asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
- "orr %0, %0, #(1 << 2)\n" /* cache enable */
- "mcr p15, 0, %0, c1, c0, 0\n"
- : : "r"(val));
-
- return 0;
-}
-early_initcall(exynos5_l2_cache_init);
-
쟳tatic int __init exynos_init(void)
{
쟰rintk(KERN_INFO "EXYNOS: Initializing architecture\n");
--
1.7.1
_______________________________________________
linux-arm-kernel mailing list
<a class="moz-txt-link-abbreviated" href="mailto:linux-arm-kernel@lists.infradead.org">linux-arm-kernel@lists.infradead.org</a>
<a class="moz-txt-link-freetext" href="http://lists.infradead.org/mailman/listinfo/linux-arm-kernel">http://lists.infradead.org/mailman/listinfo/linux-arm-kernel</a>
</pre>
</blockquote>
<pre wrap="">
--
- Joonyoung Shim
_______________________________________________
linux-arm-kernel mailing list
<a class="moz-txt-link-abbreviated" href="mailto:linux-arm-kernel@lists.infradead.org">linux-arm-kernel@lists.infradead.org</a>
<a class="moz-txt-link-freetext" href="http://lists.infradead.org/mailman/listinfo/linux-arm-kernel">http://lists.infradead.org/mailman/listinfo/linux-arm-kernel</a>
</pre>
</blockquote>
<pre wrap="">
</pre>
<br>
<fieldset class="mimeAttachmentHeader"></fieldset>
<br>
<pre wrap="">_______________________________________________
linux-arm-kernel mailing list
<a class="moz-txt-link-abbreviated" href="mailto:linux-arm-kernel@lists.infradead.org">linux-arm-kernel@lists.infradead.org</a>
<a class="moz-txt-link-freetext" href="http://lists.infradead.org/mailman/listinfo/linux-arm-kernel">http://lists.infradead.org/mailman/listinfo/linux-arm-kernel</a>
</pre>
</blockquote>
<br>
</body>
</html>