/*
 * Device Tree Generator version: 1.3
 *
 * (C) Copyright 2007-2008 Xilinx, Inc.
 * (C) Copyright 2007-2009 Michal Simek
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * CAUTION: This file is automatically generated by libgen.
 * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
 *
 * XPS project directory: macsoft5
 */

/dts-v1/;
/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "xlnx,virtex405", "xlnx,virtex";
	model = "testing";
	Generic_SDRAM: memory@0 {
		device_type = "memory";
		reg = < 0x0 0x800000 >;
	} ;
	aliases {
		serial0 = &RS232;
		serial1 = &RS232_1;
	} ;
	chosen {
		bootargs = "console=ttyUL0";
		linux,stdout-path = "/plb@0/opb@40000000/serial@40620000";
	} ;
	cpus {
		#address-cells = <1>;
		#cpus = <0x1>;
		#size-cells = <0>;
		ppc405_0: cpu@0 {
			clock-frequency = <200000000>;
			compatible = "PowerPC,405", "ibm,ppc405";
			d-cache-line-size = <0x20>;
			d-cache-size = <0x4000>;
			dcr-access-method = "native";
			dcr-controller ;
			device_type = "cpu";
			i-cache-line-size = <0x20>;
			i-cache-size = <0x4000>;
			model = "PowerPC,405";
			reg = <0>;
			timebase-frequency = <200000000>;
			xlnx,apu-control = <0xde00>;
			xlnx,apu-udi-1 = <0xa18983>;
			xlnx,apu-udi-2 = <0xa38983>;
			xlnx,apu-udi-3 = <0xa589c3>;
			xlnx,apu-udi-4 = <0xa789c3>;
			xlnx,apu-udi-5 = <0xa98c03>;
			xlnx,apu-udi-6 = <0xab8c03>;
			xlnx,apu-udi-7 = <0xad8c43>;
			xlnx,apu-udi-8 = <0xaf8c43>;
			xlnx,deterministic-mult = <0x0>;
			xlnx,disable-operand-forwarding = <0x1>;
			xlnx,mmu-enable = <0x1>;
			xlnx,pvr-high = <0x0>;
			xlnx,pvr-low = <0x0>;
		} ;
	} ;
	plb: plb@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "xlnx,plb-v34-1.02.a", "simple-bus";
		ranges ;
		Generic_SDRAM: plb-sdram@0 {
			compatible = "xlnx,plb-sdram-1.00.e";
			reg = < 0x0 0x800000 >;
			xlnx,family = "virtex4";
			xlnx,include-burst-cacheln-support = <0x1>;
			xlnx,include-highspeed-pipe = <0x1>;
			xlnx,sdram-awidth = <0xc>;
			xlnx,sdram-bank-awidth = <0x2>;
			xlnx,sdram-cas-lat = <0x2>;
			xlnx,sdram-col-awidth = <0x8>;
			xlnx,sdram-dwidth = <0x10>;
			xlnx,sdram-refresh-numrows = <0x1000>;
			xlnx,sdram-tccd = <0x1>;
			xlnx,sdram-tmrd = <0x2>;
			xlnx,sdram-tras = <0x9c40>;
			xlnx,sdram-trc = <0xfde8>;
			xlnx,sdram-trcd = <0x4e20>;
			xlnx,sdram-tref = <0x40>;
			xlnx,sdram-trefi = <0xee6b28>;
			xlnx,sdram-trfc = <0x124f8>;
			xlnx,sdram-trp = <0x4e20>;
			xlnx,sdram-trrd = <0x3a98>;
			xlnx,sdram-twr = <0x3a98>;
			xlnx,sim-init-time-ps = <0x5f5e100>;
			xlnx,use-posedge-outregs = <0x0>;
		} ;
		opb: opb@40000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "xlnx,opb-v20-1.10.c", "simple-bus";
			ranges = < 0x40000000 0x40000000 0x40000000 >;
			RS232: serial@40620000 {
				clock-frequency = "";
				compatible = "xlnx,opb-uartlite-1.00.b";
				current-speed = <115200>;
				device_type = "serial";
				interrupt-parent = <&opb_intc_0>;
				interrupts = < 5 0 >;
				port-number = <0>;
				reg = < 0x40620000 0x10000 >;
				xlnx,baudrate = <0x1c200>;
				xlnx,clk-freq = <0x5f5e100>;
				xlnx,data-bits = <0x8>;
				xlnx,odd-parity = <0x1>;
				xlnx,use-parity = <0x0>;
			} ;
			RS232_1: serial@40600000 {
				clock-frequency = "";
				compatible = "xlnx,opb-uartlite-1.00.b";
				current-speed = <115200>;
				device_type = "serial";
				interrupt-parent = <&opb_intc_0>;
				interrupts = < 4 0 >;
				port-number = <1>;
				reg = < 0x40600000 0x10000 >;
				xlnx,baudrate = <0x1c200>;
				xlnx,clk-freq = <0x5f5e100>;
				xlnx,data-bits = <0x8>;
				xlnx,odd-parity = <0x1>;
				xlnx,use-parity = <0x0>;
			} ;
			opb_intc_0: interrupt-controller@41200000 {
				#interrupt-cells = <0x2>;
				compatible = "xlnx,opb-intc-1.00.c", "xlnx,xps-intc-1.00.a";
				interrupt-controller ;
				reg = < 0x41200000 0x10000 >;
				xlnx,kind-of-intr = <0x30>;
				xlnx,num-intr-inputs = <0x6>;
			} ;
			opb_spi_0: opb-spi@55000000 {
				compatible = "xlnx,opb-spi-1.00.e";
				interrupt-parent = <&opb_intc_0>;
				interrupts = < 2 2 >;
				reg = < 0x55000000 0x10000 >;
				xlnx,depth = <0x10>;
				xlnx,dev-blk-id = <0x4>;
				xlnx,dev-mir-enable = <0x0>;
				xlnx,family = "virtex4";
				xlnx,fifo-exist = <0x1>;
				xlnx,interrupt-present = <0x1>;
				xlnx,ip-reg-bar-offset = <0x60>;
				xlnx,num-bits-reg = <0x8>;
				xlnx,num-bits-sr = <0x8>;
				xlnx,num-offchip-ss-bits = <0x4>;
				xlnx,num-ss-bits = <0x4>;
				xlnx,occupancy-num-bits = <0x4>;
				xlnx,spi-slave-only = <0x0>;
				#address-cells = <1>;
				#size-cells = <0>;
				spi_flash@0 {
					compatible = "stm,m25p32", "m25p80";
					reg = <0>;
					spi-max-frequency = <10000000>;
				};
				spi_flash@1 {
					compatible = "stm,m25p32", "m25p80";
					reg = <1>;
					spi-max-frequency = <10000000>;
					#address-cells = <1>;
					#size-cells = <1>;
					partition@0x00000000 {
						label = "test-part1";
						reg = <0x00000000 0x00400000>;
					};
				};
			} ;
		} ;
	} ;
}  ;