Both files are mostly the same. Add the deltas to irq-vic and remove irq.c Signed-off-by: Thomas Gleixner --- arch/arm/mach-msm/Kconfig | 1 arch/arm/mach-msm/Makefile | 2 arch/arm/mach-msm/irq-vic.c | 12 +++- arch/arm/mach-msm/irq.c | 111 -------------------------------------------- 4 files changed, 12 insertions(+), 114 deletions(-) Index: linux-2.6/arch/arm/mach-msm/Kconfig =================================================================== --- linux-2.6.orig/arch/arm/mach-msm/Kconfig +++ linux-2.6/arch/arm/mach-msm/Kconfig @@ -10,6 +10,7 @@ config ARCH_MSM7X00A select ARCH_MSM_ARM11 select MSM_SMD select MSM_SMD_PKG3 + select MSM_VIC select CPU_V6 select MSM_PROC_COMM select HAS_MSM_DEBUG_UART_PHYS Index: linux-2.6/arch/arm/mach-msm/Makefile =================================================================== --- linux-2.6.orig/arch/arm/mach-msm/Makefile +++ linux-2.6/arch/arm/mach-msm/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_DEBUG_FS) += clock-debug.o obj-$(CONFIG_MSM_VIC) += irq-vic.o obj-$(CONFIG_MSM_IOMMU) += iommu.o iommu_dev.o devices-iommu.o -obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o +obj-$(CONFIG_ARCH_MSM7X00A) += dma.o acpuclock-arm11.o obj-$(CONFIG_ARCH_MSM7X30) += dma.o obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o Index: linux-2.6/arch/arm/mach-msm/irq-vic.c =================================================================== --- linux-2.6.orig/arch/arm/mach-msm/irq-vic.c +++ linux-2.6/arch/arm/mach-msm/irq-vic.c @@ -43,6 +43,12 @@ #define VIC_NUM_REGS 2 #endif +#ifdef CONFIG_ARCH_MSM7X00A +# define VIC_MASTEREN_MSK 0x01 +#else +# define VIC_MASTEREN_MSK 0x03 +#endif + static inline void msm_irq_write_all_regs(unsigned long offs, unsigned int val) { int i; @@ -79,12 +85,14 @@ static __init void msm_init_gc(void __io struct irq_chip_type *ct; gc = irq_alloc_generic_chip("msm", 1, irq_start, base, handle_level_irq); - gc->wake_enabled = IRQ_MSK(32); ct = gc->chip_types; ct->chip.irq_ack = irq_gc_ack; ct->chip.irq_mask = irq_gc_mask_disable_reg; ct->chip.irq_unmask = irq_gc_unmask_enable_reg; +#ifndef CONFIG_ARCH_MSM7X00A ct->chip.irq_set_wake = irq_gc_set_wake; + gc->wake_enabled = IRQ_MSK(32); +#endif ct->chip.irq_set_type = msm_irq_set_type, ct->regs.ack = VIC_INT_CLEAR0; ct->regs.disable = VIC_INT_ENCLEAR0; @@ -116,7 +124,7 @@ void __init msm_init_irq(void) writel(0, MSM_VIC_BASE + VIC_CONFIG); /* enable interrupt controller */ - writel(3, MSM_VIC_BASE + VIC_INT_MASTEREN); + writel(VIC_MASTEREN_MSK, MSM_VIC_BASE + VIC_INT_MASTEREN); for (irq = 0; irq < NR_MSM_IRQS; irq += 32, reg_base += 4) msm_init_gc(reg_base, irq); Index: linux-2.6/arch/arm/mach-msm/irq.c =================================================================== --- linux-2.6.orig/arch/arm/mach-msm/irq.c +++ /dev/null @@ -1,111 +0,0 @@ -/* linux/arch/arm/mach-msm/irq.c - * - * Copyright (C) 2007 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include -#include -#include - -#include -#include - -#define VIC_REG(off) (MSM_VIC_BASE + (off)) - -#define VIC_INT_SELECT0 0x0000 /* 1: FIQ, 0: IRQ */ -#define VIC_INT_EN0 0x0010 -#define VIC_INT_ENCLEAR0 0x0020 -#define VIC_INT_ENSET0 0x0030 -#define VIC_INT_TYPE0 0x0040 /* 1: EDGE, 0: LEVEL */ -#define VIC_INT_POLARITY0 0x0050 /* 1: NEG, 0: POS */ -#define VIC_INT_MASTEREN 0x0064 /* 1: IRQ, 2: FIQ */ -#define VIC_CONFIG 0x0068 /* 1: USE ARM1136 VIC */ -#define VIC_INT_CLEAR0 0x00B0 - -#define VIC_NUM_REGS 2 - -static inline void msm_irq_write_all_regs(unsigned long offs, unsigned int val) -{ - int i; - - for (i = 0; i < VIC_NUM_REGS; i++) - writel(val, MSM_VIC_BASE + offs + (i * 4)); -} - -static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type) -{ - struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - u32 mask = 1 << (d->irq - gc->irq_base); - - if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING)) - gc->polarity_cache |= mask; - else - gc->polarity_cache &= ~mask; - writel(gc->polarity_cache, gc->reg_base + gc->chip_types->regs.type); - - if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { - gc->type_cache |= mask; - __irq_set_handler_locked(d->irq, handle_edge_irq); - } else { - gc->type_cache &= ~mask; - __irq_set_handler_locked(d->irq, handle_level_irq); - } - writel(gc->type_cache, gc->reg_base + gc->chip_types->regs.polarity); - return 0; -} - -static __init void msm_init_gc(void __iomem *base, unsigned int irq_start) -{ - struct irq_chip_generic *gc; - struct irq_chip_type *ct; - - gc = irq_alloc_generic_chip("msm", 1, irq_start, base, handle_level_irq); - ct = gc->chip_types; - ct->chip.irq_ack = irq_gc_ack; - ct->chip.irq_mask = irq_gc_mask_disable_reg; - ct->chip.irq_unmask = irq_gc_unmask_enable_reg; - ct->chip.irq_set_type = msm_irq_set_type, - ct->regs.ack = VIC_INT_CLEAR0; - ct->regs.disable = VIC_INT_ENCLEAR0; - ct->regs.enable = VIC_INT_ENSET0; - ct->regs.type = VIC_INT_TYPE0; - ct->regs.polarity = VIC_INT_POLARITY0; - - irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_NOREQUEST | IRQ_NOPROBE, 0); -} - -void __init msm_init_irq(void) -{ - void __iomem *reg_base = MSM_VIC_BASE; - unsigned int irq; - - /* select level interrupts */ - msm_irq_write_all_regs(VIC_INT_TYPE0, 0); - - /* select highlevel interrupts */ - msm_irq_write_all_regs(VIC_INT_POLARITY0, 0); - - /* select IRQ for all INTs */ - msm_irq_write_all_regs(VIC_INT_SELECT0, 0); - - /* disable all INTs */ - msm_irq_write_all_regs(VIC_INT_EN0, 0); - - /* don't use vic */ - writel(0, MSM_VIC_BASE + VIC_CONFIG); - - /* enable interrupt controller */ - writel(3, MSM_VIC_BASE + VIC_INT_MASTEREN); - - for (irq = 0; irq < NR_MSM_IRQS; irq += 32, reg_base += 4) - msm_init_gc(reg_base, irq); -}