sirc and irq-vic use now the same set_type function. Let sirc use the vic version. Signed-off-by: Thomas Gleixner --- arch/arm/mach-msm/include/mach/irqs.h | 3 +++ arch/arm/mach-msm/irq-vic.c | 2 +- arch/arm/mach-msm/sirc.c | 24 +----------------------- 3 files changed, 5 insertions(+), 24 deletions(-) Index: linux-2.6/arch/arm/mach-msm/include/mach/irqs.h =================================================================== --- linux-2.6.orig/arch/arm/mach-msm/include/mach/irqs.h +++ linux-2.6/arch/arm/mach-msm/include/mach/irqs.h @@ -39,4 +39,7 @@ #define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n)) #define MSM_INT_TO_REG(base, irq) (base + irq / 32) +struct irq_data; +int msm_irq_set_type(struct irq_data *d, unsigned int flow_type); + #endif Index: linux-2.6/arch/arm/mach-msm/irq-vic.c =================================================================== --- linux-2.6.orig/arch/arm/mach-msm/irq-vic.c +++ linux-2.6/arch/arm/mach-msm/irq-vic.c @@ -57,7 +57,7 @@ static inline void msm_irq_write_all_reg writel(val, MSM_VIC_BASE + offs + (i * 4)); } -static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type) +int msm_irq_set_type(struct irq_data *d, unsigned int flow_type) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); u32 mask = 1 << (d->irq - gc->irq_base); Index: linux-2.6/arch/arm/mach-msm/sirc.c =================================================================== --- linux-2.6.orig/arch/arm/mach-msm/sirc.c +++ linux-2.6/arch/arm/mach-msm/sirc.c @@ -32,28 +32,6 @@ static struct sirc_cascade_regs sirc_reg } }; -static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type) -{ - struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - u32 mask = 1 << (d->irq - gc->irq_base); - - if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING)) - gc->polarity_cache |= mask; - else - gc->polarity_cache &= ~mask; - writel(gc->polarity_cache, gc->reg_base + gc->chip_types->regs.type); - - if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { - gc->type_cache |= mask; - __irq_set_handler_locked(d->irq, handle_edge_irq); - } else { - gc->type_cache &= ~mask; - __irq_set_handler_locked(d->irq, handle_level_irq); - } - writel(gc->type_cache, gc->reg_base + gc->chip_types->regs.polarity); - return 0; -} - /* Finds the pending interrupt on the passed cascade irq and redrives it */ static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc) { @@ -82,7 +60,7 @@ static void msm_init_one_sirc(struct sir ct->chip.irq_mask = irq_gc_mask_disable_reg; ct->chip.irq_unmask = irq_gc_unmask_enable_reg; ct->chip.irq_set_wake = irq_gc_set_wake; - ct->chip.irq_set_type = sirc_irq_set_type; + ct->chip.irq_set_type = msm_irq_set_type; ct->regs.ack = SPSS_SIRC_INT_CLEAR; ct->regs.disable = SPSS_SIRC_INT_ENABLE_CLEAR; ct->regs.enable = SPSS_SIRC_INT_ENABLE_SET;