That makes it almost the same as the irq-vic code.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
 arch/arm/mach-msm/irq.c |   31 ++++++++++++++++++-------------
 1 file changed, 18 insertions(+), 13 deletions(-)

Index: linux-2.6/arch/arm/mach-msm/irq.c
===================================================================
--- linux-2.6.orig/arch/arm/mach-msm/irq.c
+++ linux-2.6/arch/arm/mach-msm/irq.c
@@ -19,8 +19,7 @@
 #include <mach/hardware.h>
 #include <mach/msm_iomap.h>
 
-#define VIC_REG_0(off) (MSM_VIC_BASE + (off))
-#define VIC_REG_1(off) (MSM_VIC_BASE + (off))
+#define VIC_REG(off) (MSM_VIC_BASE + (off))
 
 #define VIC_INT_SELECT0		0x0000		/* 1: FIQ, 0: IRQ */
 #define VIC_INT_EN0		0x0010
@@ -32,6 +31,16 @@
 #define VIC_CONFIG		0x0068		/* 1: USE ARM1136 VIC */
 #define VIC_INT_CLEAR0		0x00B0
 
+#define VIC_NUM_REGS	    2
+
+static inline void msm_irq_write_all_regs(unsigned long offs, unsigned int val)
+{
+	int i;
+
+	for (i = 0; i < VIC_NUM_REGS; i++)
+		writel(val, MSM_VIC_BASE + offs + (i * 4));
+}
+
 static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
@@ -80,26 +89,22 @@ void __init msm_init_irq(void)
 	unsigned int irq;
 
 	/* select level interrupts */
-	writel(0, VIC_REG_0(VIC_INT_TYPE0));
-	writel(0, VIC_REG_1(VIC_INT_TYPE0));
+	msm_irq_write_all_regs(VIC_INT_TYPE0, 0);
 
 	/* select highlevel interrupts */
-	writel(0, VIC_REG_0(VIC_INT_POLARITY0));
-	writel(0, VIC_REG_1(VIC_INT_POLARITY0));
+	msm_irq_write_all_regs(VIC_INT_POLARITY0, 0);
 
 	/* select IRQ for all INTs */
-	writel(0, VIC_REG_0(VIC_INT_SELECT0));
-	writel(0, VIC_REG_1(VIC_INT_SELECT0));
+	msm_irq_write_all_regs(VIC_INT_SELECT0, 0);
 
 	/* disable all INTs */
-	writel(0, VIC_REG_0(VIC_INT_EN0));
-	writel(0, VIC_REG_1(VIC_INT_EN0));
+	msm_irq_write_all_regs(VIC_INT_EN0, 0);
 
-	/* don't use 1136 vic */
-	writel(0, VIC_REG_0(VIC_CONFIG));
+	/* don't use vic */
+	writel(0, MSM_VIC_BASE + VIC_CONFIG);
 
 	/* enable interrupt controller */
-	writel(1, VIC_REG_0(VIC_INT_MASTEREN));
+	writel(3, MSM_VIC_BASE + VIC_INT_MASTEREN);
 
 	for (irq = 0; irq < NR_MSM_IRQS; irq += 32, reg_base += 4)
 		msm_init_gc(reg_base, irq);