<br><br><div class="gmail_quote">On Tue, Feb 8, 2011 at 6:50 PM, Rob Herring <span dir="ltr"><<a href="mailto:robherring2@gmail.com">robherring2@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">
<div class="im">On 02/08/2011 09:51 AM, Yong Shen wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Hi Arnaud,<br>
<br>
I also took a while to think about this before posting patches. I prefer<br>
to put it in board related code since the various PMIC used on each<br>
boards may have influence on cpuidle latency or other charactors,<br>
although it could be minor.<br>
<br>
</blockquote>
<br></div>
But you are not going to be doing voltage scaling in idle. Is it even possible to do sleeping operations like accessing a PMIC in idle?<br></blockquote><div>I guess you are asking if modes like 'state retention' are possible for idle state. so far there is no official mapping between c-states and various arm idle states, which is something linaro power management group is working on. Therefore I also treat 'state retention' as a c-state.</div>
<div><br></div><div>ps. remove lpdk in cc list to avoid auto-reply messages.</div><div>Yong</div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">
<br>
The core is powergated, so lowering voltage would not help. Doing bus scaling or DDR self-refresh are the only likely additional operations.<br><font color="#888888">
<br>
Rob<br>
</font></blockquote></div><br>