<div class="gmail_quote">On Mon, Jan 31, 2011 at 11:40 AM, Russell King - ARM Linux <span dir="ltr"><<a href="mailto:linux@arm.linux.org.uk">linux@arm.linux.org.uk</a>></span> wrote:<br><br><blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
What can happen is you receive the DATAEND interrupt,<br>
which tears down the data side of the request, and starts the stop<br>
command. Meanwhile there's still data left in the FIFO for the CPU<br>
to read.<br>
<br>
I suspect there's a similar race between DMA and the host CPU too as<br>
you leave the DATAEND interrupt on. I suspect for reliability, we<br>
need to have the DMA controller callback function in place to enable<br>
the DATAEND interrupt. Or something like that.<br>
</blockquote></div><br>Yes I get it now, well, what we do is essentially create three state<br>variables that are all checked at end of DMA (by adding a<br>DMA termination callback), end of PIO or DATAEND IRQ arrival.<br>
So a little bit like:<br><br>if (dataend && (pio_end || dma_end))<br> complete;<br><br>I'll cook up some patch ASAP, just need to backport some<br>stuff on top of your latest MMCI patches.<br><br>Linus Walleij<br>