Hi Amit,<div><br></div><div>I agree about all the comments. New patch is coming.</div><div><br></div><div>Yong</div><div><div><br><div class="gmail_quote">On Wed, Oct 13, 2010 at 6:38 PM, Amit Kucheria <span dir="ltr"><<a href="mailto:amit.kucheria@linaro.org">amit.kucheria@linaro.org</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">Yong,<br>
<br>
Some more comments. But the patch is looking good now.<br>
<div class="im"><br>
On Fri, Oct 8, 2010 at 11:08 AM, <<a href="mailto:yong.shen@linaro.org">yong.shen@linaro.org</a>> wrote:<br>
> From: Yong Shen <<a href="mailto:yong.shen@linaro.org">yong.shen@linaro.org</a>><br>
><br>
> it is tested on babbage 3.0<br>
<br>
</div>Change to<br>
<br>
"Cpufreq driver for imx51. The operating points are currently tested<br>
<div><div></div><div class="h5">on babbage 3.0."<br>
<br>
> Signed-off-by: Yong Shen <<a href="mailto:yong.shen@linaro.org">yong.shen@linaro.org</a>><br>
> ---<br>
> arch/arm/Kconfig | 6 +<br>
> arch/arm/mach-mx5/Kconfig | 1 +<br>
> arch/arm/mach-mx5/Makefile | 1 +<br>
> arch/arm/mach-mx5/board-mx51_babbage.c | 12 ++-<br>
> arch/arm/mach-mx5/clock-mx51.c | 24 ++++<br>
> arch/arm/mach-mx5/cpu.c | 2 +<br>
> arch/arm/mach-mx5/cpu_wp-mx51.c | 42 ++++++<br>
> arch/arm/mach-mx5/cpu_wp-mx51.h | 14 ++<br>
> arch/arm/plat-mxc/Makefile | 2 +<br>
> arch/arm/plat-mxc/cpufreq.c | 236 ++++++++++++++++++++++++++++++++<br>
> arch/arm/plat-mxc/include/mach/mxc.h | 20 +++-<br>
> 11 files changed, 358 insertions(+), 2 deletions(-)<br>
> create mode 100644 arch/arm/mach-mx5/cpu_wp-mx51.c<br>
> create mode 100644 arch/arm/mach-mx5/cpu_wp-mx51.h<br>
> create mode 100644 arch/arm/plat-mxc/cpufreq.c<br>
><br>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig<br>
> index d203b84..71a572a 100644<br>
> --- a/arch/arm/Kconfig<br>
> +++ b/arch/arm/Kconfig<br>
> @@ -1690,6 +1690,12 @@ if ARCH_HAS_CPUFREQ<br>
><br>
> source "drivers/cpufreq/Kconfig"<br>
><br>
> +config CPU_FREQ_IMX<br>
> + tristate "CPUfreq driver for i.MX CPUs"<br>
> + depends on ARCH_MXC && CPU_FREQ<br>
> + help<br>
> + This enables the CPUfreq driver for i.MX CPUs.<br>
> +<br>
> config CPU_FREQ_SA1100<br>
> bool<br>
><br>
> diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig<br>
> index 0848db5..7a621b4 100644<br>
> --- a/arch/arm/mach-mx5/Kconfig<br>
> +++ b/arch/arm/mach-mx5/Kconfig<br>
> @@ -5,6 +5,7 @@ config ARCH_MX51<br>
> default y<br>
> select MXC_TZIC<br>
> select ARCH_MXC_IOMUX_V3<br>
> + select ARCH_HAS_CPUFREQ<br>
><br>
> comment "MX5 platforms:"<br>
><br>
> diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile<br>
> index 86c66e7..e2af3fb 100644<br>
> --- a/arch/arm/mach-mx5/Makefile<br>
> +++ b/arch/arm/mach-mx5/Makefile<br>
> @@ -5,6 +5,7 @@<br>
> # Object file lists.<br>
> obj-y := cpu.o mm.o clock-mx51.o devices.o<br>
><br>
> +obj-$(CONFIG_CPU_FREQ_IMX) += cpu_wp-mx51.o<br>
<br>
</div></div>s/wp/op/ ?<br>
<br>
Operating point is a more widely used word for frequency/voltage pairs<br>
in the ARM world. We will also want to consider using the OPP library<br>
currently being discussed elsewhere on LAKML. So change all instances<br>
of working point or wp to operating point or op.<br>
<div class="im"><br>
> obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o<br>
> obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o<br>
> obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o<br>
> diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c<br>
> index 6e384d9..2d2a052 100644<br>
> --- a/arch/arm/mach-mx5/board-mx51_babbage.c<br>
> +++ b/arch/arm/mach-mx5/board-mx51_babbage.c<br>
> @@ -1,5 +1,5 @@<br>
> /*<br>
> - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.<br>
> + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.<br>
> * Copyright (C) 2009-2010 Amit Kucheria <<a href="mailto:amit.kucheria@canonical.com">amit.kucheria@canonical.com</a>><br>
> *<br>
> * The code contained herein is licensed under the GNU General Public<br>
> @@ -32,6 +32,7 @@<br>
> #include <asm/mach/time.h><br>
><br>
> #include "devices.h"<br>
> +#include "cpu_wp-mx51.h"<br>
><br>
> #define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */<br>
> #define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */<br>
> @@ -279,8 +280,17 @@ static struct sys_timer mxc_timer = {<br>
> .init = mx51_babbage_timer_init,<br>
> };<br>
><br>
> +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,<br>
> + char **cmdline, struct meminfo *mi)<br>
> +{<br>
> +#if defined(CONFIG_CPU_FREQ_IMX)<br>
> + get_cpu_wp = mx51_get_cpu_wp;<br>
<br>
</div>s/wp/op<br>
<div><div></div><div class="h5"><br>
> +#endif<br>
> +}<br>
> +<br>
> MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")<br>
> /* Maintainer: Amit Kucheria <<a href="mailto:amit.kucheria@canonical.com">amit.kucheria@canonical.com</a>> */<br>
> + .fixup = fixup_mxc_board,<br>
> .phys_io = MX51_AIPS1_BASE_ADDR,<br>
> .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,<br>
> .boot_params = PHYS_OFFSET + 0x100,<br>
> diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c<br>
> index 6af69de..f23cfab 100644<br>
> --- a/arch/arm/mach-mx5/clock-mx51.c<br>
> +++ b/arch/arm/mach-mx5/clock-mx51.c<br>
> @@ -39,6 +39,8 @@ static struct clk ahb_clk;<br>
> static struct clk ipg_clk;<br>
> static struct clk usboh3_clk;<br>
><br>
> +DEFINE_SPINLOCK(clk_lock);<br>
> +<br>
> #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */<br>
><br>
> static int _clk_ccgr_enable(struct clk *clk)<br>
> @@ -342,6 +344,26 @@ static unsigned long clk_arm_get_rate(struct clk *clk)<br>
> return parent_rate / div;<br>
> }<br>
><br>
> +static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate)<br>
> +{<br>
> + u32 reg, cpu_podf;<br>
> + unsigned long flags, parent_rate;<br>
> +<br>
> + parent_rate = clk_get_rate(clk->parent);<br>
> + cpu_podf = parent_rate / rate - 1;<br>
> + /* use post divider to change freq */<br>
> + spin_lock_irqsave(&clk_lock, flags);<br>
> +<br>
> + reg = __raw_readl(MXC_CCM_CACRR);<br>
> + reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;<br>
> + reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;<br>
> + __raw_writel(reg, MXC_CCM_CACRR);<br>
> +<br>
> + spin_unlock_irqrestore(&clk_lock, flags);<br>
> +<br>
> + return 0;<br>
> +}<br>
> +<br>
> static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)<br>
> {<br>
> u32 reg, mux;<br>
> @@ -694,6 +716,7 @@ static struct clk periph_apm_clk = {<br>
> static struct clk cpu_clk = {<br>
> .parent = &pll1_sw_clk,<br>
> .get_rate = clk_arm_get_rate,<br>
> + .set_rate = _clk_cpu_set_rate,<br>
> };<br>
><br>
> static struct clk ahb_clk = {<br>
> @@ -837,6 +860,7 @@ static struct clk_lookup lookups[] = {<br>
> _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)<br>
> _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)<br>
> _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)<br>
> + _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)<br>
> };<br>
><br>
> static void clk_tree_init(void)<br>
> diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c<br>
> index 2d37785..83add9c 100644<br>
> --- a/arch/arm/mach-mx5/cpu.c<br>
> +++ b/arch/arm/mach-mx5/cpu.c<br>
> @@ -22,6 +22,8 @@ static int cpu_silicon_rev = -1;<br>
><br>
> #define SI_REV 0x48<br>
><br>
> +struct cpu_wp *(*get_cpu_wp)(int *wp);<br>
> +<br>
<br>
</div></div>s/wp/op<br>
<div class="im"><br>
> static void query_silicon_parameter(void)<br>
> {<br>
> void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE);<br>
> diff --git a/arch/arm/mach-mx5/cpu_wp-mx51.c b/arch/arm/mach-mx5/cpu_wp-mx51.c<br>
> new file mode 100644<br>
> index 0000000..51bde45<br>
> --- /dev/null<br>
> +++ b/arch/arm/mach-mx5/cpu_wp-mx51.c<br>
<br>
</div>filename s/wp/op<br>
<div class="im"><br>
> @@ -0,0 +1,42 @@<br>
> +/*<br>
> + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.<br>
> + */<br>
> +<br>
> +/*<br>
> + * The code contained herein is licensed under the GNU General Public<br>
> + * License. You may obtain a copy of the GNU General Public License<br>
> + * Version 2 or later at the following locations:<br>
> + *<br>
> + * <a href="http://www.opensource.org/licenses/gpl-license.html" target="_blank">http://www.opensource.org/licenses/gpl-license.html</a><br>
> + * <a href="http://www.gnu.org/copyleft/gpl.html" target="_blank">http://www.gnu.org/copyleft/gpl.html</a><br>
> + */<br>
> +<br>
> +#include <linux/types.h><br>
> +#include <mach/hardware.h><br>
> +<br>
> +static struct cpu_wp cpu_wp_auto[] = {<br>
<br>
</div>s/cpu_wp/mx51_cpu_wp<br>
<br>
This also makes this struct explicity to mx51.<br>
<br>
> + {<br>
> + .pll_rate = 800000000,<br>
<div class="im">> + .cpu_rate = 160000000,<br>
> + .pdf = 4,<br>
> + .mfi = 8,<br>
> + .mfd = 2,<br>
> + .mfn = 1,<br>
> + .cpu_podf = 4,<br>
> + .cpu_voltage = 850000,},<br>
> + {<br>
> + .pll_rate = 800000000,<br>
> + .cpu_rate = 800000000,<br>
> + .pdf = 0,<br>
> + .mfi = 8,<br>
> + .mfd = 2,<br>
> + .mfn = 1,<br>
> + .cpu_podf = 0,<br>
> + .cpu_voltage = 1100000,},<br>
> +};<br>
<br>
</div>Except for cpu_rate and cpu_voltage, I don't see the other fields<br>
being used anywhere.<br>
<div class="im"><br>
> +struct cpu_wp *mx51_get_cpu_wp(int *wp)<br>
> +{<br>
> + *wp = sizeof(cpu_wp_auto) / sizeof(struct cpu_wp);<br>
> + return cpu_wp_auto;<br>
> +}<br>
<br>
</div>s/wp/op<br>
<div><div></div><div class="h5"><br>
> diff --git a/arch/arm/mach-mx5/cpu_wp-mx51.h b/arch/arm/mach-mx5/cpu_wp-mx51.h<br>
> new file mode 100644<br>
> index 0000000..8038b62<br>
> --- /dev/null<br>
> +++ b/arch/arm/mach-mx5/cpu_wp-mx51.h<br>
> @@ -0,0 +1,14 @@<br>
> +/*<br>
> + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.<br>
> + */<br>
> +<br>
> +/*<br>
> + * The code contained herein is licensed under the GNU General Public<br>
> + * License. You may obtain a copy of the GNU General Public License<br>
> + * Version 2 or later at the following locations:<br>
> + *<br>
> + * <a href="http://www.opensource.org/licenses/gpl-license.html" target="_blank">http://www.opensource.org/licenses/gpl-license.html</a><br>
> + * <a href="http://www.gnu.org/copyleft/gpl.html" target="_blank">http://www.gnu.org/copyleft/gpl.html</a><br>
> + */<br>
> +<br>
> +extern struct cpu_wp *mx51_get_cpu_wp(int *wp);<br>
> diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile<br>
> index 78d405e..0b8464f 100644<br>
> --- a/arch/arm/plat-mxc/Makefile<br>
> +++ b/arch/arm/plat-mxc/Makefile<br>
> @@ -16,6 +16,8 @@ obj-$(CONFIG_MXC_ULPI) += ulpi.o<br>
> obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o<br>
> obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o<br>
> obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o<br>
> +# CPU FREQ support<br>
> +obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o<br>
> ifdef CONFIG_SND_IMX_SOC<br>
> obj-y += ssi-fiq.o<br>
> obj-y += ssi-fiq-ksym.o<br>
> diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c<br>
> new file mode 100644<br>
> index 0000000..9990ea8<br>
> --- /dev/null<br>
> +++ b/arch/arm/plat-mxc/cpufreq.c<br>
> @@ -0,0 +1,236 @@<br>
> +/*<br>
> + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.<br>
> + */<br>
> +<br>
> +/*<br>
> + * The code contained herein is licensed under the GNU General Public<br>
> + * License. You may obtain a copy of the GNU General Public License<br>
> + * Version 2 or later at the following locations:<br>
> + *<br>
> + * <a href="http://www.opensource.org/licenses/gpl-license.html" target="_blank">http://www.opensource.org/licenses/gpl-license.html</a><br>
> + * <a href="http://www.gnu.org/copyleft/gpl.html" target="_blank">http://www.gnu.org/copyleft/gpl.html</a><br>
> + */<br>
> +<br>
> +/*<br>
> + * A driver for the Freescale Semiconductor i.MXC CPUfreq module.<br>
> + * The CPUFREQ driver is for controling CPU frequency. It allows you to change<br>
> + * the CPU clock speed on the fly.<br>
> + */<br>
> +<br>
> +#include <linux/types.h><br>
> +#include <linux/kernel.h><br>
> +#include <linux/cpufreq.h><br>
> +#include <linux/init.h><br>
> +#include <linux/proc_fs.h><br>
> +#include <linux/regulator/consumer.h><br>
> +#include <linux/clk.h><br>
> +#include <linux/delay.h><br>
> +#include <linux/io.h><br>
> +#include <mach/hardware.h><br>
> +#include <asm/setup.h><br>
> +#include <mach/clock.h><br>
> +#include <asm/cacheflush.h><br>
> +#include <linux/hrtimer.h><br>
> +<br>
> +static int cpu_freq_khz_min;<br>
> +static int cpu_freq_khz_max;<br>
> +static int arm_lpm_clk;<br>
> +static int arm_normal_clk;<br>
> +static int cpufreq_suspended;<br>
> +<br>
> +static struct clk *cpu_clk;<br>
> +static struct cpufreq_frequency_table *imx_freq_table;<br>
> +<br>
> +static int cpu_wp_nr;<br>
> +static struct cpu_wp *cpu_wp_tbl;<br>
> +<br>
> +static int set_cpu_freq(int freq)<br>
> +{<br>
> + int ret = 0;<br>
> + int org_cpu_rate;<br>
> + int gp_volt = 0;<br>
> + int i;<br>
> +<br>
> + org_cpu_rate = clk_get_rate(cpu_clk);<br>
> + if (org_cpu_rate == freq)<br>
> + return ret;<br>
> +<br>
> + for (i = 0; i < cpu_wp_nr; i++) {<br>
> + if (freq == cpu_wp_tbl[i].cpu_rate)<br>
> + gp_volt = cpu_wp_tbl[i].cpu_voltage;<br>
> + }<br>
> +<br>
> + if (gp_volt == 0)<br>
> + return ret;<br>
> +<br>
> + ret = clk_set_rate(cpu_clk, freq);<br>
> + if (ret != 0) {<br>
> + printk(KERN_DEBUG "cannot set CPU clock rate\n");<br>
> + return ret;<br>
> + }<br>
> +<br>
> + return ret;<br>
> +}<br>
> +<br>
> +static int mxc_verify_speed(struct cpufreq_policy *policy)<br>
> +{<br>
> + if (policy->cpu != 0)<br>
> + return -EINVAL;<br>
> +<br>
> + return cpufreq_frequency_table_verify(policy, imx_freq_table);<br>
> +}<br>
> +<br>
> +static unsigned int mxc_get_speed(unsigned int cpu)<br>
> +{<br>
> + if (cpu)<br>
> + return 0;<br>
> +<br>
> + return clk_get_rate(cpu_clk) / 1000;<br>
> +}<br>
> +<br>
> +static int mxc_set_target(struct cpufreq_policy *policy,<br>
> + unsigned int target_freq, unsigned int relation)<br>
> +{<br>
> + struct cpufreq_freqs freqs;<br>
> + int freq_Hz;<br>
> + int ret = 0;<br>
> + unsigned int index;<br>
> +<br>
> + if (cpufreq_suspended) {<br>
> + target_freq = clk_get_rate(cpu_clk) / 1000;<br>
> + cpufreq_frequency_table_target(policy, imx_freq_table,<br>
> + target_freq, relation, &index);<br>
> + freq_Hz = imx_freq_table[index].frequency * 1000;<br>
> +<br>
> + if (freq_Hz == arm_lpm_clk)<br>
> + freqs.old = cpu_wp_tbl[cpu_wp_nr - 2].cpu_rate / 1000;<br>
</div></div> ^^^^^^^^^^^^^<br>
Use an enum for the various OP names instead of depending on an<br>
operating point to be at a certain place in the table.<br>
<br>
> + else<br>
<div><div></div><div class="h5">> + freqs.old = arm_lpm_clk / 1000;<br>
> +<br>
> + freqs.new = freq_Hz / 1000;<br>
> + freqs.cpu = 0;<br>
> + freqs.flags = 0;<br>
> + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);<br>
> + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);<br>
> + return ret;<br>
> + }<br>
> +<br>
> + cpufreq_frequency_table_target(policy, imx_freq_table,<br>
> + target_freq, relation, &index);<br>
> + freq_Hz = imx_freq_table[index].frequency * 1000;<br>
> +<br>
> + freqs.old = clk_get_rate(cpu_clk) / 1000;<br>
> + freqs.new = freq_Hz / 1000;<br>
> + freqs.cpu = 0;<br>
> + freqs.flags = 0;<br>
> + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);<br>
> +<br>
> + if (freqs.old != freqs.new)<br>
> + ret = set_cpu_freq(freq_Hz);<br>
> +<br>
> + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);<br>
> +<br>
> + return ret;<br>
> +}<br>
> +<br>
> +static int __init mxc_cpufreq_init(struct cpufreq_policy *policy)<br>
> +{<br>
> + int ret;<br>
> + int i;<br>
> +<br>
> + printk(KERN_INFO "i.MXC CPU frequency driver\n");<br>
> +<br>
> + if (policy->cpu != 0)<br>
> + return -EINVAL;<br>
> +<br>
> + cpu_clk = clk_get(NULL, "cpu_clk");<br>
> + if (IS_ERR(cpu_clk)) {<br>
> + printk(KERN_ERR "%s: failed to get cpu clock\n", __func__);<br>
> + return PTR_ERR(cpu_clk);<br>
> + }<br>
> +<br>
> + /* Set the current working point. */<br>
> + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr);<br>
> +<br>
> + cpu_freq_khz_min = cpu_wp_tbl[0].cpu_rate / 1000;<br>
> + cpu_freq_khz_max = cpu_wp_tbl[0].cpu_rate / 1000;<br>
> +<br>
> + imx_freq_table = kmalloc(<br>
> + sizeof(struct cpufreq_frequency_table) * (cpu_wp_nr + 1),<br>
> + GFP_KERNEL);<br>
> +<br>
> + for (i = 0; i < cpu_wp_nr; i++) {<br>
> + imx_freq_table[i].index = i;<br>
> + imx_freq_table[i].frequency =<br>
> + cpu_wp_tbl[i].cpu_rate / 1000;<br>
> +<br>
> + if ((cpu_wp_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min)<br>
> + cpu_freq_khz_min = cpu_wp_tbl[i].cpu_rate / 1000;<br>
> +<br>
> + if ((cpu_wp_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max)<br>
> + cpu_freq_khz_max = cpu_wp_tbl[i].cpu_rate / 1000;<br>
> + }<br>
> +<br>
> + imx_freq_table[i].index = i;<br>
> + imx_freq_table[i].frequency = CPUFREQ_TABLE_END;<br>
> +<br>
> + policy->cur = clk_get_rate(cpu_clk) / 1000;<br>
> + policy->governor = CPUFREQ_DEFAULT_GOVERNOR;<br>
> + policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min;<br>
> + policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max;<br>
> +<br>
> + arm_lpm_clk = cpu_freq_khz_min * 1000;<br>
> + arm_normal_clk = cpu_freq_khz_max * 1000;<br>
> +<br>
> + /* Manual states, that PLL stabilizes in two CLK32 periods */<br>
> + policy->cpuinfo.transition_latency = 10;<br>
> +<br>
> + ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table);<br>
> +<br>
> + if (ret < 0) {<br>
> + clk_put(cpu_clk);<br>
> + printk(KERN_ERR "%s: failed to register i.MXC CPUfreq\n",<br>
> + __func__);<br>
> + return ret;<br>
> + }<br>
> +<br>
> + cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu);<br>
> + return 0;<br>
> +}<br>
> +<br>
> +static int mxc_cpufreq_exit(struct cpufreq_policy *policy)<br>
> +{<br>
> + cpufreq_frequency_table_put_attr(policy->cpu);<br>
> +<br>
> + /* Reset CPU to 665MHz */<br>
> + set_cpu_freq(arm_normal_clk);<br>
> + clk_put(cpu_clk);<br>
> + return 0;<br>
> +}<br>
> +<br>
> +static struct cpufreq_driver mxc_driver = {<br>
> + .flags = CPUFREQ_STICKY,<br>
> + .verify = mxc_verify_speed,<br>
> + .target = mxc_set_target,<br>
> + .get = mxc_get_speed,<br>
> + .init = mxc_cpufreq_init,<br>
> + .exit = mxc_cpufreq_exit,<br>
> + .name = "imx",<br>
> +};<br>
> +<br>
> +static int __devinit mxc_cpufreq_driver_init(void)<br>
> +{<br>
> + return cpufreq_register_driver(&mxc_driver);<br>
> +}<br>
> +<br>
> +static void mxc_cpufreq_driver_exit(void)<br>
> +{<br>
> + cpufreq_unregister_driver(&mxc_driver);<br>
> +}<br>
> +<br>
> +module_init(mxc_cpufreq_driver_init);<br>
> +module_exit(mxc_cpufreq_driver_exit);<br>
> +<br>
> +MODULE_AUTHOR("Freescale Semiconductor Inc. Yong Shen <<a href="mailto:yong.shen@linaro.org">yong.shen@linaro.org</a>>");<br>
> +MODULE_DESCRIPTION("CPUfreq driver for i.MX");<br>
> +MODULE_LICENSE("GPL");<br>
> diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h<br>
> index a790bf2..31df991 100644<br>
> --- a/arch/arm/plat-mxc/include/mach/mxc.h<br>
> +++ b/arch/arm/plat-mxc/include/mach/mxc.h<br>
> @@ -1,5 +1,5 @@<br>
> /*<br>
> - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.<br>
> + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.<br>
<br>
</div></div>Copyright 2004-2007,2010 ?<br>
<div class="im"><br>
> * Copyright (C) 2008 Juergen Beisert (<a href="mailto:kernel@pengutronix.de">kernel@pengutronix.de</a>)<br>
> *<br>
> * This program is free software; you can redistribute it and/or<br>
> @@ -133,6 +133,24 @@ extern unsigned int __mxc_cpu_type;<br>
> # define cpu_is_mxc91231() (0)<br>
> #endif<br>
><br>
> +#ifndef __ASSEMBLY__<br>
> +<br>
> +struct cpu_wp {<br>
<br>
</div>s/cpu_wp/mx51_cpu_wp<br>
<div><div></div><div class="h5"><br>
> + u32 pll_reg;<br>
> + u32 pll_rate;<br>
> + u32 cpu_rate;<br>
> + u32 pdr0_reg;<br>
> + u32 pdf;<br>
> + u32 mfi;<br>
> + u32 mfd;<br>
> + u32 mfn;<br>
> + u32 cpu_voltage;<br>
> + u32 cpu_podf;<br>
> +};<br>
> +<br>
> +extern struct cpu_wp *(*get_cpu_wp)(int *wp);<br>
> +#endif<br>
> +<br>
> #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)<br>
> /* These are deprecated, use mx[23][157]_setup_weimcs instead. */<br>
> #define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10))<br>
> --<br>
> 1.6.3.3<br>
</div></div></blockquote></div><br></div></div>