<br><div class="gmail_quote"><blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">The freq problem is describe here below, but it is not clear to me:<br>
<br>From <b><a href="http://www.ti.com/litv/pdf/sprufi3a" name="12987eec80487717_&lid=en_US_folder_p_tech_docs_user_guides_action_link" target="_blank">TMS320DM36x
DMSoC Multichannel Buffered Serial Port User's Guide (Rev. A)</a></b>
<br><div class="im">2.5.3 Data Clock Generation<br></div>When the receive/transmit clock mode is set to 1 (CLK(R/X)M = 1 in the pin control register (PCR)), the<br>
data clocks (CLK(R/X)) are driven by the internal sample rate generator output clock, CLKG. You can<br>
select for the receiver and transmitter from a variety of data bit clocks including:<br>• The input clock to the sample rate generator, which can be either the internal clock source or a<br>dedicated external clock source via the MCBSP_CLKX, MCBSP_CLKR, or MCBSP_CLKS pins. The<br>
McBSP internal clock is the CPU/6 clock. See Section 2.5.3.1 for details on the source of the McBSP<br>internal clock.<br>• The input clock source (internal clock source or external clock<br>MCBSP_CLKX/MCBSP_CLKR/MCBSP_CLKS) to the sample rate generator can be divided-down by a<br>
programmable value (CLKGDV bit in the sample rate generator register (SRGR)) to drive CLKG.<br>Regardless of the source to the sample rate generator, the rising edge of CLKSRG (see Figure 5)<br>generates CLKG and FSG.<br>
<br>CPU/6 is not clear.<br></blockquote><div><br>
</div></div><br>Reading better the documentation the point seems now clear.<br>We have pllc1 sysclk4 that is the clock of McBSP peripheral.<br>And so it was abviously this frequency to be used when McBSP has to generate the clock.<br>
Sorry..<br><br>Raffaele<br><br><br>