Hello Nicolas.<br>Thanks a lot for your answer!<br><br>My intention was to use for ATA/CF.<br>How do you think is it worth to do?<br><br>If the DMAC is not so powerful why it exists?<br>Best regards,<br>Valentin.<br><br><br>
<div class="gmail_quote">On Wed, Jan 13, 2010 at 4:16 PM, Nicolas Ferre <span dir="ltr"><<a href="mailto:nicolas.ferre@atmel.com">nicolas.ferre@atmel.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
Le 13/01/2010 13:20, Haavard Skinnemoen :<br>
<div class="im">> Hi,<br>
><br>
> The DMA Controller is very configurable, and I am not familiar with how<br>
> it is configured on the SAM9 devices. I'm Cc'ing one of our SAM9 gurus;<br>
> hopefully he can help you.<br>
><br>
> Haavard<br>
><br>
> (fullquoting so that Nicolas can see your questions)<br>
><br>
> Valentin Sitdikov <<a href="mailto:v.sitdikov@gmail.com">v.sitdikov@gmail.com</a>> wrote:<br>
>> Hello Haavard.<br>
>><br>
>> Could you please comment something on my problem?<br>
>><br>
>> Currently i am working on getting at91sam9263 dmac working under demaenige<br>
>> framework.<br>
>> So I have investigating that it is a kind of copy Synopsys DesignWare DMA<br>
>> Controller which is used in AVR32.<br>
>> But there is at least one difference:<br>
>> AVR32 BLOCK_TS is 11 bit wide but at91sam9263 BLOCK_TS is 5 bit size<br>
>> So your driver is working on at91sam9263 taking in to account this<br>
>> difference.<br>
>><br>
>> As you can imagine to have such a small dma transaction is not quite<br>
>> convenient.<br>
>> May be you can recommend something to overcome 5 bit restriction?<br>
<br>
</div>As you noted, AT91SAM9263 has significantly reduced block size for<br>
transfers, this lead into max transfer size of 124B in a single block<br>
transfer:<br>
ref. DMAC_CTLxL field SRC_TR_WIDTH (32 bits)<br>
DMAC_CTLxH with BLOCK_TS (5 bits) , Max value = 31<br>
<br>
Single Block Size = Max_Block_TS (31) * Max_TR_Width (4) = 124B<br>
<br>
Unless you loop on a reduced set of addresses, we usually consider it as<br>
not so useful (you finally find it less resource consuming to retrieve<br>
data using CPU power).<br>
<br>
I have no workaround for this.<br>
A dirty way to do mem2mem transfer is to use a peripheral in loopback<br>
mode with PDC (SPI loopback for instance). But I suppose you will get<br>
quite poor performance)...<br>
<div class="im"><br>
>> There is also bit field in config register which is called MAX_ABRST the<br>
>> meaning of<br>
>> which is not quite clear. It is 10 bits long,<br>
>> So why it 10 bits long if BLOCK_TS only 5 bits long?<br>
>> What real meaning has it ?<br>
<br>
</div>It is related to the burst length that the AHB master can request on the<br>
internal bus (here the AHB master is the DMA controller itself): in<br>
short, in case of internal bus availability, the total amount of data<br>
that this master can transfer on the internal bus without stopping burst.<br>
It has nothing to do with the internal possibilities of the DMA controller.<br>
<br>
Best regards,<br>
--<br>
<font color="#888888">Nicolas Ferre<br>
<br>
</font></blockquote></div><br>