[PATCH v2 4/6] arm64: dts: ti: k3-j784s4-j742s2-main-common: Assign SRAM to VPU nodes

[Kumar, Udit]

On 8/11/2026 2:22 AM, Brandon Brnich wrote:
> The Wave5 VPU supports connecting to on-chip SRAM through its secondary
> AXI interface. This allows temporal buffers to be stored on a per-stream
> basis, reducing DDR memory traffic.
> 
> Signed-off-by: Brandon Brnich <b-brnich at ti.com>
> Reviewed-by: Andrew Davis <afd at ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> index e836f0f42e30d..21ec9f207ff63 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> @@ -1002,6 +1002,7 @@ vpu0: video-codec at 4210000 {
>  		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
>  		clocks = <&k3_clks 241 2>;
>  		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
> +		sram = <&main_navss_sram>;
>  	};
>  
>  	vpu1: video-codec at 4220000 {
> @@ -1010,6 +1011,7 @@ vpu1: video-codec at 4220000 {
>  		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
>  		clocks = <&k3_clks 242 2>;
>  		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
> +		sram = <&main_navss_sram>;
>  	};

Hello Brandon,
Could you check, how two instances of hardware can share same sram ?

LTM, each block need 64KB of SRAM
https://elixir.bootlin.com/linux/v7.2.2/source/drivers/media/platform/chips-media/wave5/wave5-vpu.c#L463


>  
>  	main_sdhci0: mmc at 4f80000 {