[net] net: airoha: enable RX_DONE interrupt for RX queue 31

[Simon Horman]

On Thu, Sep 03, 2026 at 12:19:25AM +0200, Lorenzo Bianconi wrote:
> > Thank you for your contribution! Sashiko AI review found 1 potential
> > issue(s) to consider:
> > 
> > Critical: 0 · High: 1 · Medium: 0 · Low: 0
> > 
> > - [High] Incomplete fix: the patch only adds BIT(31) to
> >   RX_IRQ1_BANK_PIN_MASK, so the exact defect the commit message…
> > 
> > --
> > 
> > net: airoha: enable RX_DONE interrupt for RX queue 31
> > 
> > This adds BIT(31) to RX_IRQ1_BANK_PIN_MASK so that RX queue 31's RX_DONE
> > interrupt is routed to IRQ bank 1.  The stated goal is that the queue gets
> > drained and its buffers returned to the page pool.
> > 
> > > diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
> > > index fa9a8edce22f..8277c1c87bb3 100644
> > > --- a/drivers/net/ethernet/airoha/airoha_eth.h
> > > +++ b/drivers/net/ethernet/airoha/airoha_eth.h
> > > @@ -538,7 +538,7 @@ struct airoha_wdma_info {
> > >  
> > >  /* RX queue to IRQ mapping: BIT(q) in IRQ(n) */
> > >  #define RX_IRQ0_BANK_PIN_MASK			0x839f
> > > -#define RX_IRQ1_BANK_PIN_MASK			0x7fe00000
> > > +#define RX_IRQ1_BANK_PIN_MASK			0xffe00000
> > >  #define RX_IRQ2_BANK_PIN_MASK			0x20
> > >  #define RX_IRQ3_BANK_PIN_MASK			0x40
> > 
> > [Severity: High]
> > Does this leave the same problem in place for the other RX rings?  After the
> > change the union of the four bank masks is:
> > 
> >   0x839f | 0xffe00000 | 0x20 | 0x40 = 0xffe083ff
> > 
> > so rings 0-9, 15 and 21-31 are covered, but bits 10-14 and 16-20 are still
> > clear in every bank mask.
> 
> Here I wanted just to align to the vendor sdk and enable rx queues 24-31 (31
> was missing) in preparation for HW GRO support. The other rx queues are
> out-of-scope.

Thanks Lorenzo,

Seems reasonable to me.

Reviewed-by: Simon Horman <horms at kernel.org>