[PATCH v2 0/8] Add Aspeed AST2700 SDRAM EDAC support

[Borislav Petkov]

On Mon, Aug 24, 2026 at 10:42:27AM +0800, Ryan Chen wrote:
> Add ECC error reporting for the Aspeed AST2700 SoC to the existing
> aspeed_edac driver.
> 
> The AST2700 memory controller keeps the same overall EDAC programming
> model as the earlier Aspeed BMC SoCs, but uses a different register
> layout, a split interrupt status/clear/mask scheme and DDR4/DDR5 memory.
> Rather than fork the driver, the existing code is first tidied and
> generalised, then the AST2700 is added as one more per-SoC variant.
> 
> Patches 2-5 are bug fixes and cleanups to the existing driver. Patches 6
> and 7 rework the implementation to accommodate the AST2700. Patch 8 adds
> the AST2700 support itself.

Sashiko has comments:

https://sashiko.dev/#/patchset/20260824-edac-v2-0-c8d8bb693586%40aspeedtech.com

Please address them: if valid, fix them, if not, explain why they don't need
to be fixed.

Btw, I don't see Stefan reviewing this driver and his last mail on LKML is
from 2025 so it looks like we'll orphan this driver too.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette