[PATCH 1/2] clk: rockchip: rk3399: add 85.5 MHz rate to PLL rate table

[Alexey Charkov]

Hi Vasily,

On Wed, Sep 2, 2026 at 3:42 AM Vasily Khoruzhick <anarsoul at gmail.com> wrote:
>
> 85.5 MHz is the pixel clock of the standard DMT 1366x768 at 60 mode,
> which is the native mode of many cheap HDMI panels.
>
> Use a 1368 MHz VCO (24 MHz * 57, already used by the existing
> 1368 MHz entry) with postdiv1 = postdiv2 = 4 to hit 85.5 MHz
> exactly in integer mode.
>
> Assisted-by: Claude:claude-fable-5
> Signed-off-by: Vasily Khoruzhick <anarsoul at gmail.com>
> ---
>  drivers/clk/rockchip/clk-rk3399.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
> index c2b243d7a5e2..db241d2df625 100644
> --- a/drivers/clk/rockchip/clk-rk3399.c
> +++ b/drivers/clk/rockchip/clk-rk3399.c
> @@ -98,6 +98,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
>         RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
>         RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),
>         RK3036_PLL_RATE(  96000000, 1, 64, 4, 4, 1, 0),
> +       RK3036_PLL_RATE(  85500000, 1, 57, 4, 4, 1, 0),

There is already an entry for 1368000000, which is 16x your rate, and
the 16x divisor should fit comfortably into the downstream clock's
8-bit divisor field. Do you really need a separate PLL rate? Have you
checked what the hardware arrives at with the unmodified PLL table -
e.g. via /sys/kernel/debug/clk/clk_summary?

Best regards,
Alexey