[PATCH v2 7/8] hwtracing: hisi_ptt: Add pattern PMU config for trace format selection

[Sizhe Liu]

On 2026/9/1 9:31, Yushan Wang wrote:
> On 8/27/2026 10:04 PM, Sizhe Liu wrote:
>> Introduce a `pattern` PMU config field (config:36-39) that controls
>> which TLP header format the hardware traces. bit[3:1] are reserved for
>> future extension and only bit0 is used currently:
>>
>> - pattern=0 (default, compatibility mode): the driver sets bit[8] of
>>     HISI_PTT_TRACE_CTRL so the hardware traces the data in compatibility
>>     mode.
>> - pattern=1: the driver clears bit[8] of HISI_PTT_TRACE_CTRL so the
>>     hardware traces the data pattern including some bitfields of the TLP
>>     header defined in PCIe r6.4 sec 2.2.1.2.
>>
>> Note that bit[8] of HISI_PTT_TRACE_CTRL is inverted with respect to the
>> `pattern` value: bit[8]=1 selects the legacy format, bit[8]=0 selects
>> the new format. Bit[11:9] is still reserved, which is consistent with the
>> PMU config field. The driver validates the 4-bit value in
>> hisi_ptt_trace_valid_pattern() and applies it in hisi_ptt_trace_start().
>>
>> Document the new parameter in Documentation/trace/hisi-ptt.rst.
>>
>> Signed-off-by: Sizhe Liu <liusizhe5 at huawei.com>
>> ---
>>    Documentation/trace/hisi-ptt.rst | 25 +++++++++++++++++++++++--
>>    drivers/hwtracing/ptt/hisi_ptt.c | 25 ++++++++++++++++++++++++-
>>    drivers/hwtracing/ptt/hisi_ptt.h |  4 ++++
>>    3 files changed, 51 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/trace/hisi-ptt.rst b/Documentation/trace/hisi-ptt.rst
>> index f6a2655f99e5..c95eaa12f4d3 100644
>> --- a/Documentation/trace/hisi-ptt.rst
>> +++ b/Documentation/trace/hisi-ptt.rst
>> @@ -255,7 +255,28 @@ directly from the TLP header.
>>         DW2 [                     Header DW2                            ]
>>         DW3 [                     Header DW3                            ]
>>
>> -5. Memory Management
>> +5. Trace pattern
>> +-----------------
>> +
>> +You can control whether the trace is taken with the new version of the
>> +TLP header format by specifying the `pattern` parameter. The default
>> +value is 0, which means the legacy format is used for backward
>> +compatibility. The parameter value is 4 bit and bit[3:1] are currently
>> +reserved for extension. Current supported values are shown below:
>> +
>> +- 4'b0000: legacy trace format
>> +    DW2 and DW3 are printed with generic field names only, and
>> +    no message-type-basedfield decoding.
>> +- 4'b0001: trace format v1
>> +    DW2 and DW3 are decoded according to the TLP message type (MWr,
>> +    Msg, Atomic, IO, CPL, Cfg) with detailed field names. It is recommended to
>> +    use trace format v1 when the current PCIe link generation is higher than
>> +    PCIe 6.0.
>> +
>> +For trace data recorded by an older tracer without the `pattern` parameter,
>> +the decoder will work as `pattern` forced to 0.
>> +
>> +6. Memory Management
>>    --------------------
>>
>>    The traced TLP headers will be written to the memory allocated
>> @@ -274,7 +295,7 @@ will commit the AUX buffer first and then apply for a new one with
>>    the same size. The size of AUX buffer is default to 16MiB. User can
>>    adjust the size by specifying the `-m` parameter of the perf command.
>>
>> -6. Decoding
>> +7. Decoding
>>    -----------
>>
>>    You can decode the traced data with `perf report -D` command (currently
>> diff --git a/drivers/hwtracing/ptt/hisi_ptt.c b/drivers/hwtracing/ptt/hisi_ptt.c
>> index 94c371c49135..1696c30ac4c9 100644
>> --- a/drivers/hwtracing/ptt/hisi_ptt.c
>> +++ b/drivers/hwtracing/ptt/hisi_ptt.c
>> @@ -233,6 +233,10 @@ static int hisi_ptt_trace_start(struct hisi_ptt *hisi_ptt)
>>         val |= FIELD_PREP(HISI_PTT_TRACE_CTRL_TARGET_SEL, hisi_ptt->trace_ctrl.filter);
>>         if (!hisi_ptt->trace_ctrl.is_port)
>>                 val |= HISI_PTT_TRACE_CTRL_FILTER_MODE;
>> +     if (!ctrl->pattern)
>> +             val |= HISI_PTT_TRACE_CTRL_PATTERN;
>> +     else
>> +             val &= ~HISI_PTT_TRACE_CTRL_PATTERN;
> 
> Hi Sizhe,
> 
> This hunk seems not able to be applied to mainstream cleanly, otherwise
> this series LGTM.
> 
> Reviewed-by: Yushan Wang <wangyushan12 at huawei.com>
> 
Hi Yushan,

I will fix it in v3. Thanks for your Reviewed-by tag.

Regards,
Sizhe >>
>>
>>         /* Start the Trace */
>>         val |= HISI_PTT_TRACE_CTRL_EN;
>> @@ -805,12 +809,14 @@ PMU_FORMAT_ATTR(filter,         "config:0-19");
>>    PMU_FORMAT_ATTR(direction,   "config:20-23");
>>    PMU_FORMAT_ATTR(type,                "config:24-31");
>>    PMU_FORMAT_ATTR(format,              "config:32-35");
>> +PMU_FORMAT_ATTR(pattern,             "config:36-39");
>>
>>    static struct attribute *hisi_ptt_pmu_format_attrs[] = {
>>         &format_attr_filter.attr,
>>         &format_attr_direction.attr,
>>         &format_attr_type.attr,
>>         &format_attr_format.attr,
>> +     &format_attr_pattern.attr,
>>         NULL
>>    };
>>
> 
> [...]