[PATCH v2 2/2] perf: RISC-V: store available counter mask as bitmap

[Paul Walmsley]

Hi,

On Tue, 18 Aug 2026, Xixin Liu wrote:

> The available-counter mask was a single unsigned long, but iteration
> uses RISCV_MAX_COUNTERS, which is 64. On RV32 that reads past the object.
> Filling with an unsigned-long bit at index 32 and above is also wrong.
> 
> Use DECLARE_BITMAP and set_bit/bitmap helpers. Walk each bitmap word
> into CFG_MATCH when checking events, when allocating an index, and when
> stopping all counters. Set the counter base to i times BITS_PER_LONG.
> Share the CFG_MATCH ecall through a small helper so the 32-bit argument
> split is not duplicated. On qemu-system-riscv32 the probe bitmap has bits
> above XLEN set, so the first word alone is not enough.

This patch results in several 'checkpatch.pl --strict' "check" messages.
I've fixed them in the queued patches, but please run 'checkpatch.pl 
--strict' next time.

thanks,


- Paul