[PATCH 0/8] i3c: mipi-i3c-hci: Add Aspeed AST2700 support

[Billy Tsai]

The Aspeed AST2700 SoC integrates an I3C host controller based on the
MIPI I3C HCI v1.1 programming model, extended with an in-house control
block and a PHY programming window. Both extra register regions are
advertised through a standard HCI vendor extended capability. This
series teaches the existing mipi-i3c-hci driver to drive the AST2700
controller without forking the driver.

The AST2700 specifics are expressed in two ways:

 - Deviations from generic HCI protocol behavior are expressed as
   individual quirks in the match data: the existing
   HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET, plus three new quirks for
   address-indexed DAT slots (HCI_QUIRK_DAT_INDEX_IS_ADDR), 64-bit DMA
   addressing (HCI_QUIRK_DMA_64BIT) and clearing the TX start threshold
   in DMA mode (HCI_QUIRK_TX_START_THLD).

 - Everything that depends on the ASPEED vendor capability actually
   being present -- programming the vendor register blocks (master
   mode init, PHY timing, the interrupt summary path, the IBI
   termination threshold and the DAA index registers), and selecting
   the IRQ handler and IRQF_SHARED at request_irq() time -- is keyed to
   is_aspeed(), a single explicit check set from the devicetree
   compatible in probe().

Generic MIPI I3C HCI controllers are unaffected.

The series is organised as follows:

 - Patch 1 documents the devicetree binding.

 - Patches 2-4 add the generic HCI quirks AST2700 needs --
   address-indexed DAT slots, 64-bit DMA addressing, and clearing the
   TX start threshold in DMA mode -- with no AST2700-specific code yet;
   nothing sets these quirks until patch 5.

 - Patch 5 ties it together: it recognizes the ASPEED vendor extended
   capability, brings the controller up for transfers (master mode,
   PHY timing, reset/clock resources, the interrupt summary path,
   master clock stall), and enables the quirks from patches 2-4 plus
   HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET for the
   "aspeed,ast2700-i3c-hci" compatible.

 - Patch 6 adds the IBI termination threshold, a safeguard against a
   misbehaving device that never terminates a payload IBI on its own.

 - Patches 7-8 tune bus behaviour: PIO TX queue utilization, and the
   PHY's built-in pull-ups for boards without external resistors.

Tested on an AST2700 EVB: the controller probes in DMA/PIO mode,
completes DAA and runs CCC, IBI and private transfers.

Assisted-by: Claude:claude-fable-5
Signed-off-by: Billy Tsai <billy_tsai at aspeedtech.com>
---
Billy Tsai (8):
      dt-bindings: i3c: Document the AST2700 I3C controller
      i3c: mipi-i3c-hci: Support address-indexed DAT slots
      i3c: mipi-i3c-hci: Add a quirk for 64-bit DMA addressing
      i3c: mipi-i3c-hci: Add a quirk to clear the TX start threshold
      i3c: mipi-i3c-hci: Add support for the AST2700 I3C controller
      i3c: mipi-i3c-hci: Program AST2700 IBI termination threshold
      i3c: mipi-i3c-hci: Improve AST2700 PIO TX queue utilization
      i3c: mipi-i3c-hci: Support the AST2700 internal pull-ups

 .../bindings/i3c/aspeed,ast2700-i3c-hci.yaml       | 133 +++++++
 drivers/i3c/master/mipi-i3c-hci/Makefile           |   2 +-
 drivers/i3c/master/mipi-i3c-hci/cmd_v1.c           |  56 ++-
 drivers/i3c/master/mipi-i3c-hci/core.c             | 229 ++++++++++--
 drivers/i3c/master/mipi-i3c-hci/dat.h              |   5 +-
 drivers/i3c/master/mipi-i3c-hci/dat_v1.c           |  63 +++-
 drivers/i3c/master/mipi-i3c-hci/ext_caps.c         |  15 +
 drivers/i3c/master/mipi-i3c-hci/ext_caps.h         |   1 +
 drivers/i3c/master/mipi-i3c-hci/hci.h              |   3 +
 drivers/i3c/master/mipi-i3c-hci/pio.c              | 122 ++-----
 drivers/i3c/master/mipi-i3c-hci/pio.h              | 109 ++++++
 drivers/i3c/master/mipi-i3c-hci/vendor_aspeed.c    | 383 +++++++++++++++++++++
 drivers/i3c/master/mipi-i3c-hci/vendor_aspeed.h    | 191 ++++++++++
 13 files changed, 1167 insertions(+), 145 deletions(-)
---
base-commit: 97f3c8379f91af507cbc3d491b87633f0583febc
change-id: 20260714-b4-i3c-hci-ast2700-bad726e20c01

Best regards,
-- 
Billy Tsai <billy_tsai at aspeedtech.com>