[RFC PATCH v4 01/16] iommu/arm-smmu-v3: Discover RME support and realm IRQ topology

[Aneesh Kumar K.V]

Nicolin Chen <nicolinc at nvidia.com> writes:

> On Mon, Apr 27, 2026 at 02:23:29PM +0530, Aneesh Kumar K.V (Arm) wrote:
>> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-realm.c
>> @@ -0,0 +1,124 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (C) 2026 ARM Ltd.
>> + */
>> +
>> +#include <linux/interrupt.h>
>> +#include <asm/rmi_smc.h>
>> +#include <asm/rmi_cmds.h>
>> +
>> +#include "arm-smmu-v3.h"
>> +
>> +#define	RMI_PSMMU_IRQ_GERROR	BIT(0)
>> +#define	RMI_PSMMU_IRQ_EVENTQ	BIT(1)
>> +#define	RMI_PSMMU_IRQ_PRIQ	BIT(2)
>> +#define	RMI_PSMMU_IRQ_CMDQ	BIT(3)
> [...]
>> +	if (irq == smmu->realm_evtq_irq)
>> +		notify_flags =  RMI_PSMMU_IRQ_EVENTQ;
>> +	else if (irq == smmu->realm_gerr_irq)
>> +		notify_flags =  RMI_PSMMU_IRQ_GERROR;
>> +	else if (irq == smmu->realm_pri_irq)
>> +		notify_flags =  RMI_PSMMU_IRQ_PRIQ;
>
> These are defined as BIT(x)...
>
>> +		if (rmi_psmmu_irq_notify(smmu->base_phys,
>> +					 notify_flags, &event)) {
> [...]
>> +			rmi_psmmu_event_consume(smmu->base_phys, notify_flags);
>
> .. and passed to RMI_PSMMU_IRQ_NOTIFY and RMI_PSMMU_EVENT_CONSUME.
>
> RMI_PSMMU_IRQ_NOTIFY takes RmiPsmmuIrqSet type, which is a 4-bit
> field that has a range of [BIT(0), BIT(3)]. So this is correct.
>
> However, RMI_PSMMU_EVENT_CONSUME takes RmiPsmmuIrq type, which is
> a 2-bit field that has a range of [0x0, 0x3]. So this seems wrong.
>

Updated that to

#define	RMI_PSMMU_IRQ_PEND_GERROR	BIT(0)
#define	RMI_PSMMU_IRQ_PEND_EVENTQ	BIT(1)
#define	RMI_PSMMU_IRQ_PEND_PRIQ		BIT(2)
#define	RMI_PSMMU_IRQ_PEND_CMDQ		BIT(3)


#define	RMI_PSMMU_IRQ_GERROR	0
#define	RMI_PSMMU_IRQ_EVENTQ	1
#define	RMI_PSMMU_IRQ_PRIQ	2
#define	RMI_PSMMU_IRQ_CMDQ	3


and 
	if (irq == smmu->realm.evtq_irq) {
		notify_flags =  RMI_PSMMU_IRQ_PEND_EVENTQ;
		psmmu_irq = RMI_PSMMU_IRQ_EVENTQ;
	} else if (irq == smmu->realm.gerr_irq) {

...
	rmi_psmmu_event_consume(smmu->base_phys, psmmu_irq);

>
>> +void arm_smmu_setup_realm_irqs(struct arm_smmu_device *smmu)
>> +{
>> +	int irq, ret;
>> +
>> +	irq = smmu->realm_evtq_irq;
>> +	if (irq) {
>> +		ret = devm_request_threaded_irq(smmu->dev, irq, NULL,
>> +						arm_smmu_realm_notify_thread,
>> +						IRQF_ONESHOT,
>> +						"arm-smmu-v3-realm-evtq",
>> +						smmu);
>
> These IRQ numbers are raw numbers forwarded by firmware and then
> returned by RMI_PSMMU_INFO:
>
> +		if ((psmmu_info->flags & RMI_PSMMU_IRQCFG_MASK) ==
> +		    RMI_PSMMU_IRQCFG_IRQ_WIRED) {
> +			smmu->realm_gerr_irq = psmmu_info->gerror_intr_num;
> +			smmu->realm_evtq_irq = psmmu_info->eventq_intr_num;
> +			smmu->realm_pri_irq = psmmu_info->priq_intr_num;
>
> Should they be converted to Linux IRQ numbers before forwarded to
> devm_request_threaded_irq?
>

Yes, that needs conversion. I guess we can use the irq_domain associated
with the non-Realm IRQ number to create the mappings?

Something like:


+static struct irq_domain *arm_smmu_get_wired_irq_domain(struct arm_smmu_device *smmu)
+{
+	int irqs[] = {
+		smmu->combined_irq,
+		smmu->evtq.q.irq,
+		smmu->gerr_irq,
+		smmu->priq.q.irq,
+	};
+	struct irq_domain *domain = NULL;
+	struct irq_data *irq_data;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(irqs); i++) {
+		if (irqs[i] <= 0)
+			continue;
+
+		irq_data = irq_get_irq_data(irqs[i]);
+		if (!irq_data || !irq_data->domain)
+			return ERR_PTR(-EINVAL);
+
+		if (domain && domain != irq_data->domain)
+			return ERR_PTR(-EINVAL);
+
+		domain = irq_data->domain;
+	}
+
+	return domain ?: ERR_PTR(-ENXIO);
+}

>
>> @@ -782,6 +787,9 @@ struct arm_smmu_device {
>>  
>>  	int				gerr_irq;
>>  	int				combined_irq;
>> +	int				realm_gerr_irq;
>> +	int				realm_evtq_irq;
>> +	int				realm_pri_irq;
>
> Nit: this series adds a few realm-specific things in the top SMMU
> structure. Maybe a "struct arm_realm_psmmu" can make them clearer.
>

Added

struct arm_smmu_realm {
	int				gerr_irq;
	int				evtq_irq;
	int				pri_irq;
	struct mutex			mutex;
	refcount_t			users;
};

-aneesh