[PATCH v3 03/14] perf cs-etm: Break branch history when instruction memory is unavailable
Leo Yan
leo.yan at arm.com
Fri Oct 30 08:13:10 PDT 2026
The decoder currently ignores OCSD_GEN_TRC_ELEM_ADDR_NACC, allowing a
subsequent range to be paired with stale branch history from before the
unreadable code.
Treat an inaccessible instruction address as a discontinuity and flush
the pending range and branch history before processing subsequent
elements.
Reviewed-by: James Clark <james.clark at linaro.org>
Signed-off-by: Leo Yan <leo.yan at arm.com>
---
tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
index b56cf57a68c88de4686ecc8b0c7e71ac0f1d2f09..3fbb3fdf0382705bd4efa732c54ebb816144b2a8 100644
--- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
+++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
@@ -594,7 +594,8 @@ static ocsd_datapath_resp_t cs_etm_decoder__gen_trace_elem_printer(
if (type == OCSD_GEN_TRC_ELEM_EO_TRACE ||
type == OCSD_GEN_TRC_ELEM_NO_SYNC ||
- type == OCSD_GEN_TRC_ELEM_TRACE_ON)
+ type == OCSD_GEN_TRC_ELEM_TRACE_ON ||
+ type == OCSD_GEN_TRC_ELEM_ADDR_NACC)
resp = cs_etm_decoder__buffer_discontinuity(etmq, packet_queue,
trace_chan_id);
else if (type == OCSD_GEN_TRC_ELEM_INSTR_RANGE)
--
2.34.1
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