[PATCH v5 2/2] cache: add SMCCC-backed cache invalidate provider
Conor Dooley
conor at kernel.org
Thu Oct 29 16:21:50 PDT 2026
On Wed, Oct 21, 2026 at 10:45:57PM +0000, Srirangan Madhavan wrote:
> Add a cache maintenance provider for the cache clean+invalidate interface
> defined by Arm DEN0028 v1.7.
>
> Register the interface attributes function as an SMCCC device and bind the
> provider through the SMCCC bus. The provider reads the firmware attributes
> during probe and serializes cache maintenance calls. It handles transient
> BUSY and RATE_LIMITED responses with bounded retries. It also registers
> with the generic cache coherency framework used by memregion callers.
>
> Signed-off-by: Srirangan Madhavan <smadhavan at nvidia.com>
> Reviewed-by: Jonathan Cameron <jonathan.cameron at oss.qualcomm.com>
I acked this on v3, but I don't see it here or a reason for why it
isn't. Ultimately, you're only harming yourself but still.
Unless the arm64 guys pipe up and expect me to take this,
Acked-by: Conor Dooley <conor.dooley at microchip.com>
because it's so tied to arm architectural stuff.
Cheers,
Conor.
> ---
> drivers/cache/Kconfig | 11 +++
> drivers/cache/Makefile | 2 +
> drivers/cache/arm_smccc_cache.c | 156 ++++++++++++++++++++++++++++++++
> drivers/firmware/smccc/smccc.c | 5 +
> 4 files changed, 174 insertions(+)
> create mode 100644 drivers/cache/arm_smccc_cache.c
>
> diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
> index 1518449d47b5..57fd1823dec5 100644
> --- a/drivers/cache/Kconfig
> +++ b/drivers/cache/Kconfig
> @@ -42,6 +42,17 @@ menuconfig CACHEMAINT_FOR_HOTPLUG
>
> if CACHEMAINT_FOR_HOTPLUG
>
> +config ARM_SMCCC_CACHE
> + bool "Arm SMCCC cache maintenance provider"
> + depends on ARM64 && HAVE_ARM_SMCCC_DISCOVERY
> + help
> + Enable support for the Arm SMCCC cache clean+invalidate
> + interface as a provider for memory hotplug-like cache
> + maintenance operations.
> + The provider registers only when firmware advertises the
> + SMCCC calls and attributes, so systems without firmware support
> + continue without this registered provider.
> +
> config HISI_SOC_HHA
> tristate "HiSilicon Hydra Home Agent (HHA) device driver"
> depends on (ARM64 && ACPI) || COMPILE_TEST
> diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
> index b3362b15d6c1..55736a032d6f 100644
> --- a/drivers/cache/Makefile
> +++ b/drivers/cache/Makefile
> @@ -4,4 +4,6 @@ obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o
> obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o
> obj-$(CONFIG_STARFIVE_STARLINK_CACHE) += starfive_starlink_cache.o
>
> +# Providers below depend on CACHEMAINT_FOR_HOTPLUG.
> +obj-$(CONFIG_ARM_SMCCC_CACHE) += arm_smccc_cache.o
> obj-$(CONFIG_HISI_SOC_HHA) += hisi_soc_hha.o
> diff --git a/drivers/cache/arm_smccc_cache.c b/drivers/cache/arm_smccc_cache.c
> new file mode 100644
> index 000000000000..abe6881f3de3
> --- /dev/null
> +++ b/drivers/cache/arm_smccc_cache.c
> @@ -0,0 +1,156 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2026 NVIDIA Corporation
> + *
> + * Arm SMCCC cache maintenance provider using the cache clean+invalidate
> + * interface defined by Arm DEN0028 v1.7.
> + */
> +
> +#include <linux/arm-smccc.h>
> +#include <linux/arm-smccc-bus.h>
> +#include <linux/cache_coherency.h>
> +#include <linux/cleanup.h>
> +#include <linux/container_of.h>
> +#include <linux/delay.h>
> +#include <linux/errno.h>
> +#include <linux/math.h>
> +#include <linux/minmax.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/nmi.h>
> +#include <linux/time64.h>
> +#include <linux/types.h>
> +
> +#define SMCCC_CACHE_MAX_RETRIES 5
> +#define SMCCC_CACHE_DEFAULT_DELAY_US 1000UL
> +#define SMCCC_CACHE_MAX_DELAY_US 20000UL
> +
> +struct smccc_cache {
> + /* Must be first member */
> + struct cache_coherency_ops_inst cci;
> + struct mutex lock; /* Serializes SMCCC cache maintenance calls. */
> + u64 rate_limit;
> +};
> +
> +static int smccc_cache_status_to_errno(s32 status)
> +{
> + switch (status) {
> + case SMCCC_RET_SUCCESS:
> + return 0;
> + case SMCCC_RET_NOT_SUPPORTED:
> + return -EOPNOTSUPP;
> + case SMCCC_RET_INVALID_PARAMETER:
> + return -EINVAL;
> + case SMCCC_RET_RATE_LIMITED:
> + return -EAGAIN;
> + case SMCCC_RET_BUSY:
> + return -EBUSY;
> + default:
> + return -EIO;
> + }
> +}
> +
> +static unsigned long smccc_cache_delay_us(const struct smccc_cache *cache)
> +{
> + unsigned long delay_us = 0;
> +
> + if (cache->rate_limit)
> + delay_us = DIV_ROUND_UP_ULL(USEC_PER_SEC, cache->rate_limit);
> +
> + /*
> + * Firmware may not advertise a rate limit; use a small bounded backoff
> + * instead of retrying in a tight loop.
> + */
> + if (!delay_us)
> + delay_us = SMCCC_CACHE_DEFAULT_DELAY_US;
> +
> + return min(delay_us, SMCCC_CACHE_MAX_DELAY_US);
> +}
> +
> +static int smccc_cache_wbinv(struct cache_coherency_ops_inst *cci,
> + struct cc_inval_params *invp)
> +{
> + struct smccc_cache *cache = container_of(cci, struct smccc_cache, cci);
> + unsigned long delay_us = smccc_cache_delay_us(cache);
> + struct arm_smccc_res res = {};
> + int ret;
> +
> + if (!invp->size)
> + return -EINVAL;
> +
> + /*
> + * Serialize the full retry sequence. With the default bounds, a caller
> + * may hold the mutex across up to five 20ms backoff sleeps.
> + */
> + guard(mutex)(&cache->lock);
> +
> + for (unsigned int i = 0; i < SMCCC_CACHE_MAX_RETRIES; i++) {
> + /* Long firmware operations can trigger watchdog checks. */
> + touch_nmi_watchdog();
> +
> + arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION,
> + invp->addr, invp->size, 0UL, &res);
> +
> + ret = smccc_cache_status_to_errno((s32)res.a0);
> + if (!ret)
> + return 0;
> +
> + if (ret != -EBUSY && ret != -EAGAIN)
> + return ret;
> +
> + fsleep(delay_us);
> + }
> +
> + return ret;
> +}
> +
> +static const struct cache_coherency_ops smccc_cache_ops = {
> + .wbinv = smccc_cache_wbinv,
> +};
> +
> +static int smccc_cache_probe(struct arm_smccc_device *sdev)
> +{
> + struct arm_smccc_res res = {};
> + struct smccc_cache *cache;
> + int ret;
> +
> + arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION_ATTRIBUTES,
> + &res);
> + if ((s32)res.a0)
> + return -ENODEV;
> +
> + cache = cache_coherency_ops_instance_alloc(&smccc_cache_ops,
> + struct smccc_cache, cci);
> + if (!cache)
> + return -ENOMEM;
> +
> + mutex_init(&cache->lock);
> + cache->rate_limit = res.a3;
> +
> + ret = cache_coherency_ops_instance_register(&cache->cci);
> + if (ret) {
> + mutex_destroy(&cache->lock);
> + cache_coherency_ops_instance_put(&cache->cci);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct arm_smccc_device_id smccc_cache_id_table[] = {
> + { .func_id = ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION_ATTRIBUTES },
> + {}
> +};
> +MODULE_DEVICE_TABLE(arm_smccc, smccc_cache_id_table);
> +
> +static struct arm_smccc_driver smccc_cache_driver = {
> + .name = KBUILD_MODNAME,
> + .probe = smccc_cache_probe,
> + .id_table = smccc_cache_id_table,
> +};
> +module_arm_smccc_driver(smccc_cache_driver);
> +
> +MODULE_IMPORT_NS("CACHE_COHERENCY");
> +MODULE_AUTHOR("Srirangan Madhavan");
> +MODULE_DESCRIPTION("Arm SMCCC cache maintenance provider");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/firmware/smccc/smccc.c b/drivers/firmware/smccc/smccc.c
> index 5dc768ac4143..5a5d50d17410 100644
> --- a/drivers/firmware/smccc/smccc.c
> +++ b/drivers/firmware/smccc/smccc.c
> @@ -100,6 +100,11 @@ static const struct smccc_device_info smccc_devices[] __initconst = {
> .requires_smc = true,
> .device_name = "arm-rsi",
> },
> + {
> + .func_id = ARM_SMCCC_ARCH_CLEAN_INV_MEMREGION_ATTRIBUTES,
> + .requires_smc = false,
> + .device_name = "arm-smccc-cache",
> + },
> };
>
> static bool __init smccc_probe_smccc_device(const struct smccc_device_info *smccc_dev)
> --
> 2.43.0
>
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