[PATCH v9 10/25] iommu/arm-smmu-v3-kvm: Add SMMUv3 driver

[Nicolin Chen]

On Thu, Oct 15, 2026 at 08:08:41PM +0000, Mostafa Saleh wrote:
> From: Jean-Philippe Brucker <jean-philippe at linaro.org>
> 
> Add the skeleton of the Arm SMMUv3 driver at EL2, and build the shared
> IDR/STE code and lib/hweight.o into the hypervisor.
> 
> The kernel driver, added next, fills an array describing the SMMUv3s in
> the system and hands it to the hypervisor. At init the hypervisor takes
> ownership of the array and of the SMMU MMIO regions, so the host cannot
> change either after de-privilege.
> 
> Signed-off-by: Jean-Philippe Brucker <jean-philippe at linaro.org>
> Signed-off-by: Mostafa Saleh <smostafa at google.com>

Reviewed-by: Nicolin Chen <nicolinc at nvidia.com>

With some nits:

> +/**
> + * struct hyp_arm_smmu_v3_device - SMMUv3 instance owned by the hypervisor
> + * @mmio_addr:		Physical address of the SMMU registers
> + * @mmio_size:		Size of the register region
> + * @base:		Hypervisor virtual address of the registers
> + * @features:		ARM_SMMU_FEAT_* bits
> + * @options:		ARM_SMMU_OPT_* bits
> + * @oas:		Output address size
> + * @pgsize_bitmap:	Supported page sizes
> + * @sid_bits:		Number of StreamID bits

Better drop those tabs, following

Documentation/doc-guide/kernel-doc.rst

Structure, union, and enumeration documentation:

  /**
   * struct struct_name - Brief description.
   * @member1: Description of member1.
   * @member2: Description of member2.
   *           One can provide multiple line descriptions
   *           for members.
   *
   * Description of the structure.
   */

> + *
> + * @mmio_addr, @mmio_size and ARM_SMMU_FEAT_COHERENCY are filled by the host
> + * before de-privilege, the rest by the hypervisor driver.
> + */
> +struct hyp_arm_smmu_v3_device {
> +	phys_addr_t		mmio_addr;
> +	size_t			mmio_size;
> +	void __iomem		*base;
> +	u32			features;
> +	u32			options;
> +	unsigned long		oas;
> +	unsigned long		pgsize_bitmap;
> +	unsigned int		sid_bits;

I'd drop the tabs too.

Nicolin