[PATCH 4/4] arm64: dts: imx8ulp-evk: enable HiFi4 DSP device

[shengjiu.wang at oss.nxp.com]

From: Shengjiu Wang <shengjiu.wang at nxp.com>

Add a new `&dsp` node that references the required clocks,
clock-parents, clock-rates and the `memory-region` property pointing to
the three shared buffers (vdev0vring0, vdev0vring1, vdev0buffer) and
the reserved DSP region (`dsp_reserved`).  Enable the third MU
(`&mu3`) which provides the mailbox used by the DSP.

Signed-off-by: Shengjiu Wang <shengjiu.wang at nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
index fdf3aab2224b..e253b99c2097 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -61,6 +61,27 @@ rsc_table: rsc-table at 20000000 {
 			no-map;
 		};
 
+		dsp_reserved: dsp_reserved at 8e000000 {
+			reg = <0 0x8e000000 0 0x1000000>;
+			no-map;
+		};
+
+		dsp_vdev0vring0: vdev0vring0 at 8fef0000 {
+			reg = <0 0x8fef0000 0 0x8000>;
+			no-map;
+		};
+
+		dsp_vdev0vring1: vdev0vring1 at 8fef8000 {
+			reg = <0 0x8fef8000 0 0x8000>;
+			no-map;
+		};
+
+		dsp_vdev0buffer: vdev0buffer at 8ff00000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x8ff00000 0 0x100000>;
+			no-map;
+		};
+
 		vdev0vring0: vdev0vring0 at aff00000 {
 			reg = <0 0xaff00000 0 0x8000>;
 			no-map;
@@ -145,6 +166,15 @@ &cm33 {
 	status = "okay";
 };
 
+&dsp {
+	assigned-clocks = <&cgc2 IMX8ULP_CLK_HIFI_SEL>, <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>;
+	assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD0>;
+	assigned-clock-rates = <0>, <475200000>;
+	memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,
+			<&dsp_vdev0vring1>, <&dsp_reserved>;
+	status = "okay";
+};
+
 &flexspi2 {
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&pinctrl_flexspi2_ptd>;
@@ -321,6 +351,10 @@ &mu {
 	status = "okay";
 };
 
+&mu3 {
+	status = "okay";
+};
+
 &iomuxc1 {
 	pinctrl_enet: enetgrp {
 		fsl,pins = <
-- 
2.34.1