[PATCH 07/11] dt-bindings: clock: renesas,r8a78000-cpg: Add PWM clocks

[Laurent Pinchart]

On Wed, Oct 28, 2026 at 03:43:42PM +0100, Geert Uytterhoeven wrote:
> On Wed, 28 Oct 2026 at 14:29, Laurent Pinchart wrote:
> > On Mon, Oct 26, 2026 at 03:55:23PM +0100, Geert Uytterhoeven wrote:
> > > Add definitions for the clocks used by the PWM modules on R-Car X5H:
> > >  - R8A78000_CPG_SGASYNCD16_PERW_MAIN,
> > >  - R8A78000_CPG_S0ASYNCD8_PERW_MAIN.
> > > Include R8A78000_CPG_SGASYNCD8_PERW_MAIN for ordering consistency.
> > >
> > > Signed-off-by: Geert Uytterhoeven <geert+renesas at glider.be>
> 
> > > --- a/include/dt-bindings/clock/renesas,r8a78000-cpg.h
> > > +++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
> > > @@ -28,5 +28,8 @@
> > >  #define R8A78000_CPG_SGD8_PERW_BUS           18
> > >  #define R8A78000_CPG_SGD32_PERW_BUS          19
> > >  #define R8A78000_CPG_S0D24_HSCN_OTHER                20
> > > +#define R8A78000_CPG_SGASYNCD8_PERW_MAIN     21
> > > +#define R8A78000_CPG_SGASYNCD16_PERW_MAIN    22
> >
> > Could you also add R8A78000_CPG_SGASYNCD4_PERW_MAIN and
> > R8A78000_CPG_SGASYNCD32_PERW_MAIN for ordering consistency ? The
> > dependency patch should then also include R8A78000_CPG_SGD4_PERW_BUS and
> > R8A78000_CPG_SGD16_PERW_BUS, as well as
> > R8A78000_CPG_S0D{1,2,4,8,12,16}_HSCN_OTHER.
> 
> I could add them, but do you have any need to refer to them from DT?
> So far I only added clocks that are listed as clock supplies of on-SoC
> modules, e.g. R8A78000_CPG_SGASYNCD8_PERW_MAIN is supplied to the
> Timer Unit (TMU)).

So we have two conflicting goals here. One of them is to only add clocks
that we have validated to exist (and ideally work as documented). The
other is to keep renesas,r8a78000-cpg.h readable. We won't be able to
satisfy them both fully.

I think we previously discussed adding whole groups of dividers in one
go, as some sort of middle-ground approach. Those are clocks that are
not directly controllable. There's a risk of adding clocks that don't
exist, or clocks that we won't need to reference from DT (because
they're only used as parents of the MDLC-controlled module clock). Do
you think that's an issue, could it cause ABI problems in the future ?

-- 
Regards,

Laurent Pinchart