[PATCH 2/2] clk: meson: s4: propagate rate requests through the CEC 32k muxes

[christian.koever-draxl at student.uibk.ac.at]

From: Christian Stefan Kövér-Draxl <ckoever at outlook.de>

The AO-CEC driver asks its core clock for 32768 Hz. On S4 that request
stops at ceca_32k_sel / cecb_32k_sel: both are muxes without
CLK_SET_RATE_PARENT, so it never reaches the dual divider that can
produce the rate, and probe fails with

  meson-ao-cec fe044000.cec: core clock set rate failed
  meson-ao-cec fe044000.cec: CEC controller registration failed

The equivalent G12A mux, ao_cec_sel, carries the flag, which is why CEC
works there. Add it to both S4 selectors.

The other parent of these muxes is the RTC clock, which must not be
reprogrammed on behalf of CEC, so boards should pin the mux parent to
the dual divider with assigned-clock-parents.

Only the CECA path was tested; CECB is the same defect in the
duplicated block.

Fixes: 57b55c76aaf1 ("clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller")
Signed-off-by: Christian Stefan Kövér-Draxl <ckoever at outlook.de>
---
 drivers/clk/meson/s4-peripherals.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peripherals.c
index 329cd526749e..8e303db6154c 100644
--- a/drivers/clk/meson/s4-peripherals.c
+++ b/drivers/clk/meson/s4-peripherals.c
@@ -407,6 +407,7 @@ static struct clk_regmap s4_ceca_32k_sel = {
 			&s4_rtc_clk.hw
 		},
 		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -514,6 +515,7 @@ static struct clk_regmap s4_cecb_32k_sel = {
 			&s4_rtc_clk.hw
 		},
 		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
-- 
2.56.0