[PATCH v3 1/3] dt-bindings: arm: cpus: Add brcm,bca-smp enable method

[William Zhang]

On Thu, Oct 22, 2026 at 7:15 AM Rob Herring <robh at kernel.org> wrote:
>
> On Wed, Oct 21, 2026 at 05:09:52PM +0200, Linus Walleij wrote:
> > BCMBCA systems booted through CFE can release a secondary CPU by
> > writing its ARM-state entry address to a 32-bit MMIO mailbox and
> > sending a wakeup interrupt.
> >
> > Document brcm,bca-smp and its single-cell cpu-release-addr property.
> > The boot CPU does not need a mailbox; secondary CPUs do. Add a
> > Cortex-A7 example showing both CPU nodes.
> >
> > Suggested-by: William Zhang <william.zhang at broadcom.com>
> > Signed-off-by: Linus Walleij <linusw at kernel.org>
> > ---
> >  Documentation/devicetree/bindings/arm/cpus.yaml | 36 +++++++++++++++++++++++++
> >  1 file changed, 36 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
> > index 5be89c584026..6771b85f757b 100644
> > --- a/Documentation/devicetree/bindings/arm/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
> > @@ -255,6 +255,7 @@ properties:
> >            - amlogic,meson8b-smp
> >            - arm,realview-smp
> >            - aspeed,ast2600-smp
> > +          - brcm,bca-smp
> >            - brcm,bcm11351-cpu-method
> >            - brcm,bcm23550
> >            - brcm,bcm2836-smp
> > @@ -471,6 +472,20 @@ allOf:
> >      then:
> >        required:
> >          - secondary-boot-reg
> > +  - if:
> > +      properties:
> > +        enable-method:
> > +          const: brcm,bca-smp
> > +      required:
> > +        - enable-method
> > +    then:
> > +      properties:
> > +        cpu-release-addr:
> > +          $ref: /schemas/types.yaml#/definitions/uint32
> > +          description:
> > +            Physical address of the 32-bit MMIO mailbox read by CFE after
> > +            a wakeup interrupt. Required on secondary CPUs. The kernel
> > +            writes the ARM-state entry address before sending the interrupt.
>
> required:
>   - cpu-release-addr
>
> ??? But cpu0 doesn't have an address. Is there really no address or you
> just omitted because you don't really need it. Should still be there in
> the latter case IMO.
>
> Alternatively, add the enable-method value to the existing section that
> does this. Also, there might be other cases that are a 32-bit address
> and need this same constraint.
>
Cpu0 does not need release because it is the boot up CPU.  But there
is no harm to add it to be consistent.
All the BCA v7 chips only use 32 bit address for MMIO register.
Otheriwse,
Reviewed-by: William Zhang <william.zhang at broadcom.com>

> >    - if:
> >        properties:
> >          enable-method:
> > @@ -712,4 +727,25 @@ examples:
> >          cpu-release-addr = <0 0x20000000>;
> >        };
> >      };
> > +  - |
> > +    // Example 5 (Broadcom BCMBCA with CFE):
> > +    cpus {
> > +      #size-cells = <0>;
> > +      #address-cells = <1>;
> > +
> > +      cpu at 0 {
> > +        device_type = "cpu";
> > +        compatible = "arm,cortex-a7";
> > +        reg = <0>;
> > +        enable-method = "brcm,bca-smp";
> > +      };
> > +
> > +      cpu at 1 {
> > +        device_type = "cpu";
> > +        compatible = "arm,cortex-a7";
> > +        reg = <1>;
> > +        enable-method = "brcm,bca-smp";
> > +        cpu-release-addr = <0xff800568>;
> > +      };
> > +    };
> >  ...
> >
> > --
> > 2.56.0
> >
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