[PATCH 3/7] arm64: dts: renesas: r8a78000: Add GPIO controller nodes

[Geert Uytterhoeven]

From: Marek Vasut <marek.vasut+renesas at mailbox.org>

Add device nodes for the General-Purpose Input/Output Ports (GPIO) on
the Renesas R-Car X5H (R8A78000) SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
Co-developed-by: Geert Uytterhoeven <geert+renesas at glider.be>
Signed-off-by: Geert Uytterhoeven <geert+renesas at glider.be>
---
Changes compared to Marek's original:
  - Use hardware clocks/power-domains/resets instead of direct SCMI
    references,
  - Drop gpio-ranges properties for now, as upstream lacks Pin Function
    Controller (PFC) support.
---
 arch/arm64/boot/dts/renesas/r8a78000.dtsi | 155 ++++++++++++++++++++++
 1 file changed, 155 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index 66eec0907b34fa58..36a4fa1e032ee703 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -1263,6 +1263,161 @@ pfc: pinctrl at c1080000 {
 			bootph-all;
 		};
 
+		gpio0: gpio at c1080110 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc1080110 0 0xc0>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SCPBUSD16_SCP_MAIN>;
+			power-domains = <&mdlc_aon R8A78000_MDLC_PD_AON 0x20>;
+			resets = <&mdlc_aon 0x20>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio1: gpio at c1080910 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc1080910 0 0xc0>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SCPBUSD16_SCP_MAIN>;
+			power-domains = <&mdlc_aon R8A78000_MDLC_PD_AON 0x20>;
+			resets = <&mdlc_aon 0x20>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio2: gpio at c1081110 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc1081110 0 0xc0>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SCPBUSD16_SCP_MAIN>;
+			power-domains = <&mdlc_aon R8A78000_MDLC_PD_AON 0x20>;
+			resets = <&mdlc_aon 0x20>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio3: gpio at c0800110 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc0800110 0 0xc0>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_S0D24_PERE_MAIN>;
+			power-domains = <&mdlc_pere R8A78000_MDLC_PD_APL 0x30>;
+			resets = <&mdlc_pere 0x30>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio4: gpio at c0800910 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc0800910 0 0xc0>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_S0D24_PERE_MAIN>;
+			power-domains = <&mdlc_pere R8A78000_MDLC_PD_APL 0x30>;
+			resets = <&mdlc_pere 0x30>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio5: gpio at c0400110 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc0400110 0 0xc0>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD32_PERW_BUS>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x30>;
+			resets = <&mdlc_perw 0x30>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio6: gpio at c0400910 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc0400910 0 0xc0>;
+			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD32_PERW_BUS>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x30>;
+			resets = <&mdlc_perw 0x30>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio7: gpio at c0401110 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc0401110 0 0xc0>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD32_PERW_BUS>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x30>;
+			resets = <&mdlc_perw 0x30>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio8: gpio at c0401910 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc0401910 0 0xc0>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD32_PERW_BUS>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x30>;
+			resets = <&mdlc_perw 0x30>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-reserved-ranges = <16 10>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio9: gpio at c9b00110 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc9b00110 0 0xc0>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_S0D24_HSCN_OTHER>;
+			power-domains = <&mdlc_hscn R8A78000_MDLC_PD_APL 0x50>;
+			resets = <&mdlc_hscn 0x50>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio10: gpio at c9b00910 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc9b00910 0 0xc0>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_S0D24_HSCN_OTHER>;
+			power-domains = <&mdlc_hscn R8A78000_MDLC_PD_APL 0x50>;
+			resets = <&mdlc_hscn 0x50>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
 		cpg: clock-controller at c1320000 {
 			compatible = "renesas,r8a78000-cpg";
 			reg = <0 0xc1320000 0 0x10000>;
-- 
2.43.0