[PATCH v9 10/20] dt-bindings: riscv: add Counter delegation ISA extensions description
Anup Patel
anup at brainfault.org
Fri Oct 23 07:32:35 PDT 2026
On Fri, Aug 7, 2026 at 1:39 PM Atish Patra <atish.patra at linux.dev> wrote:
>
> From: Atish Patra <atishp at rivosinc.com>
>
> Add description for the Smcdeleg/Ssccfg extension.
>
> Signed-off-by: Atish Patra <atishp at rivosinc.com>
> Acked-by: Conor Dooley <conor.dooley at microchip.com>
> Link: https://patch.msgid.link/20260701-counter_delegation-v8-10-7909f863a645@meta.com
> Signed-off-by: Paul Walmsley <pjw at kernel.org>
LGTM.
Reviewed-by: Anup Patel <anup at brainfault.org>
Regards,
Anup
> ---
> .../devicetree/bindings/riscv/extensions.yaml | 41 ++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index eee65cf73d6c..24efd3e1cf8e 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -181,6 +181,13 @@ properties:
> changes to interrupts as frozen at commit ccbddab ("Merge pull
> request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
>
> + - const: smcdeleg
> + description: |
> + The standard Smcdeleg machine-level extension for the machine mode
> + to delegate the hpmcounters to supervisor mode so that they are
> + directly accessible in the supervisor mode as ratified in the
> + 20240213 version of the privileged ISA specification.
> +
> - const: smcntrpmf
> description: |
> The standard Smcntrpmf machine-level extension for the machine mode
> @@ -220,6 +227,14 @@ properties:
> behavioural changes to interrupts as frozen at commit ccbddab
> ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
>
> + - const: ssccfg
> + description: |
> + The standard Ssccfg supervisor-level extension for configuring
> + the delegated hpmcounters to be accessible directly in supervisor
> + mode as ratified in the 20240213 version of the privileged ISA
> + specification. This extension depends on Sscsrind, Smcdeleg, Zihpm,
> + Zicntr extensions.
> +
> - const: ssccptr
> description: |
> The standard Ssccptr extension for main memory (cacheability and
> @@ -1135,6 +1150,32 @@ properties:
> allOf:
> - const: zilsd
> - const: zca
> + # Smcdeleg depends on Sscsrind, Zihpm, Zicntr
> + - if:
> + contains:
> + const: smcdeleg
> + then:
> + allOf:
> + - contains:
> + const: sscsrind
> + - contains:
> + const: zihpm
> + - contains:
> + const: zicntr
> + # Ssccfg depends on Smcdeleg, Sscsrind, Zihpm, Zicntr
> + - if:
> + contains:
> + const: ssccfg
> + then:
> + allOf:
> + - contains:
> + const: smcdeleg
> + - contains:
> + const: sscsrind
> + - contains:
> + const: zihpm
> + - contains:
> + const: zicntr
>
> allOf:
> # Zcf extension does not exist on rv64
>
> --
> 2.53.0-Meta
>
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