[PATCH v2 2/4] KVM: arm64: pkvm: Fix missing reset of GICv3 LRs

[Fuad Tabba]

On Fri, 23 Oct 2026 at 08:59, Vincent Donnefort <vdonnefort at google.com> wrote:
[..]
> > Could you say here what happens to a guest when an LR isn't reset, as I
> > asked on v1? Without this series, on QEMU changed to leave a pending
> > vINTID 100 in the top LR at CPU reset, the guest warns "Unexpected
> > interrupt (irqnr 100)". With only the EOI bit set there, the npVM
> > doesn't print anything in 150 seconds, since the maintenance interrupt
> > is asserted on every entry. With that in the message, could you also
> > bring back the Cc: stable you had on v1?
>
> Sorry I missed that.
>
> Actually I don't know if this should be backported. I believe it was working
> until now because all SoCs do reset their LRs even though they don't have to do
> it.

Fair enough, I'm fine with leaving the Cc: stable off.

Cheers,
/fuad